diff --git a/src/soc/intel/pantherlake/chip.h b/src/soc/intel/pantherlake/chip.h
index 1b6b0aecb3..bfd307553b 100644
--- a/src/soc/intel/pantherlake/chip.h
+++ b/src/soc/intel/pantherlake/chip.h
@@ -457,6 +457,20 @@ struct soc_intel_pantherlake_config {
 	 */
 	uint16_t icc_max[MAX_PTL_SKUS][NUM_VR_DOMAINS];
 
+	/*
+	 * Power State Current Thresholds for VR Domains.
+	 *
+	 * These arrays define the current thresholds for different power states (PS1,
+	 * PS2, PS3) for each Voltage Regulator (VR) domain.
+	 *
+	 * Each value is defined in 1/4 A increments.  For example, a value of 400
+	 * corresponds to 100A. The valid range is 0-512 (0-128A).  A value of 0
+	 * indicates AUTO (use default).
+	 */
+	uint16_t ps1_threshold[NUM_VR_DOMAINS];
+	uint16_t ps2_threshold[NUM_VR_DOMAINS];
+	uint16_t ps3_threshold[NUM_VR_DOMAINS];
+
 	/*
 	 * SerialIO device mode selection:
 	 * PchSerialIoDisabled,
diff --git a/src/soc/intel/pantherlake/romstage/fsp_params.c b/src/soc/intel/pantherlake/romstage/fsp_params.c
index c0dd691836..04cd86d7a1 100644
--- a/src/soc/intel/pantherlake/romstage/fsp_params.c
+++ b/src/soc/intel/pantherlake/romstage/fsp_params.c
@@ -357,6 +357,15 @@ static void fill_fspm_vr_config_params(FSP_M_CONFIG *m_cfg,
 		m_cfg->TdcMode[i] = config->tdc_mode[i];
 		m_cfg->TdcTimeWindow[i] = config->tdc_time_window_ms[i];
 	}
+
+	for (size_t i = 0; i < ARRAY_SIZE(config->ps1_threshold); i++) {
+		if (config->ps1_threshold[i])
+			m_cfg->Ps1Threshold[i] = config->ps1_threshold[i];
+		if (config->ps2_threshold[i])
+			m_cfg->Ps2Threshold[i] = config->ps2_threshold[i];
+		if (config->ps3_threshold[i])
+			m_cfg->Ps3Threshold[i] = config->ps3_threshold[i];
+	}
 }
 
 #if CONFIG(PLATFORM_HAS_EARLY_LOW_BATTERY_INDICATOR)