From 1c571446ec1402f4908aae1eb714d779f337acbe Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Wed, 27 Aug 2025 23:07:25 +0530 Subject: [PATCH] soc/intel/common/block/systemagent: Increase MTRR region size to 32 MiB MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch increases the hardcoded MTRR region size from 16 MiB to 32 MiB. This ensures a larger portion of memory is cached after the DRAM phase, which helps in avoiding performance issues in memory-constrained boots like the pre-DRAM stage. This change is crucial for optimal system performance. TEST=Able to boot google/fatcat and save 13ms of the boot time. w/o this patch: ``` 31:device enumeration 1,183,804 (13,341) ``` w/ this patch: ``` 31:device enumeration 1,159,612 (359) ``` Change-Id: I25463f1b9e3b82b1a05a8fb7a44df4d188b4731a Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/88971 Reviewed-by: Kapil Porwal Tested-by: build bot (Jenkins) Reviewed-by: Pranava Y N Reviewed-by: Jérémy Compostella --- src/soc/intel/common/block/systemagent/memmap.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/common/block/systemagent/memmap.c b/src/soc/intel/common/block/systemagent/memmap.c index ca9f680195..3b0fb6e8ae 100644 --- a/src/soc/intel/common/block/systemagent/memmap.c +++ b/src/soc/intel/common/block/systemagent/memmap.c @@ -65,7 +65,7 @@ void fill_postcar_frame(struct postcar_frame *pcf) /* * We need to make sure ramstage will be run cached. At this * point exact location of ramstage in cbmem is not known. - * Instruct postcar to cache 16 megs below cbmem top which is + * Instruct postcar to cache 32 megs below cbmem top which is * a safe bet to cover ramstage. */ printk(BIOS_DEBUG, "top_of_ram = 0x%lx\n", top_of_ram); @@ -77,7 +77,7 @@ void fill_postcar_frame(struct postcar_frame *pcf) if (ENV_CREATES_CBMEM && CONFIG(SOC_INTEL_COMMON_BASECODE_RAMTOP)) update_ramtop(top_of_ram); - postcar_frame_add_mtrr(pcf, top_of_ram - 16 * MiB, 16 * MiB, MTRR_TYPE_WRBACK); + postcar_frame_add_mtrr(pcf, top_of_ram - 32 * MiB, 32 * MiB, MTRR_TYPE_WRBACK); /* Cache the TSEG region */ postcar_enable_tseg_cache(pcf);