From 1b5f1055959ef0574c81c5d55eea75a0f22a46cd Mon Sep 17 00:00:00 2001 From: Megha Verma Date: Thu, 13 Nov 2025 14:29:50 +0530 Subject: [PATCH] mb/google/ocelot/var/ocelot: disable ISH UART0 RX pin On WCL RVP, ISH (Intel Sensor Hub) shares UART with FPS (Finger Print Sensor), we can enable either ISH UART or FPS UART, or disable both UART by changing the DIP switch settings. When DIP switch is not set for ISH, ISH RX signal is disconnected, causing ISH low power mode failure. Therefore, NC ISH RX pin mux to minimize the impact on ISH PM. As a result, ISH console won't accept input since this pin is not connected. BUG=b:428084925 TEST=DIP SW1317 3-6, 4-5 on WCL RVP DT card ON to enable FPS UART, ISH main firmware boots up and runs successfully. SW1317 all switches OFF to disable both FPS and ISH UART, ISH main firmware boots up and runs successfully. Put system into suspend state and resume back. System enters into low power mode as substate_residencies are updated. Verified using console command "cat /sys/kernel/debug/pmc_core/substate_residencies". Change-Id: I1165e0151c0a6d0e82038215703626e863739b39 Signed-off-by: Megha Verma Reviewed-on: https://review.coreboot.org/c/coreboot/+/90022 Tested-by: build bot (Jenkins) Reviewed-by: Bhat D, Krishna P Reviewed-by: P, Usha --- src/mainboard/google/ocelot/variants/ocelot/fw_config.c | 4 ---- src/mainboard/google/ocelot/variants/ocelot/gpio.c | 2 ++ 2 files changed, 2 insertions(+), 4 deletions(-) diff --git a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c index b299a406f2..e89c59482f 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/fw_config.c +++ b/src/mainboard/google/ocelot/variants/ocelot/fw_config.c @@ -392,8 +392,6 @@ static const struct pad_config ish_disable_pads[] = { PAD_NC(GPP_B22, NONE), /* GPP_B23: ISH_GP_6_SNSR_HDR */ PAD_NC(GPP_B23, NONE), - /* GPP_D05: ISH_UART0_ECAIC_RXD */ - PAD_NC(GPP_D05, NONE), /* GPP_D06: ISH_UART0_ECAIC_TXD */ PAD_NC(GPP_D06, NONE), /* GPP_F23: SMC_LID / ISH_GP9A*/ @@ -413,8 +411,6 @@ static const struct pad_config ish_enable_pads[] = { PAD_CFG_NF(GPP_B22, NONE, DEEP, NF4), /* GPP_B23: ISH_GP_6_SNSR_HDR */ PAD_CFG_NF(GPP_B23, NONE, DEEP, NF4), - /* GPP_D05: ISH_UART0_ECAIC_RXD */ - PAD_CFG_NF(GPP_D05, NONE, DEEP, NF2), /* GPP_D06: ISH_UART0_ECAIC_TXD */ PAD_CFG_NF(GPP_D06, NONE, DEEP, NF2), /* GPP_F23: SMC_LID / ISH_GP9A*/ diff --git a/src/mainboard/google/ocelot/variants/ocelot/gpio.c b/src/mainboard/google/ocelot/variants/ocelot/gpio.c index 405a424600..9166668efb 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/gpio.c +++ b/src/mainboard/google/ocelot/variants/ocelot/gpio.c @@ -135,6 +135,8 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_D02, 0, DEEP), /* GPP_D03: X4_SLOT_WAKE_N */ PAD_CFG_GPI_SCI_LOW(GPP_D03, NONE, DEEP, LEVEL), + /* GPP_D05: disable ISH_UART0_RXD */ + PAD_NC(GPP_D05, NONE), /* GPP_D07: ISH_UART0_RTS_N_SNSR_HDR */ PAD_NC(GPP_D07, NONE), /* GPP_D08: ISH_UART0_CTS_N_SNSR_HDR */