diff --git a/src/soc/intel/alderlake/chip.h b/src/soc/intel/alderlake/chip.h
index 040b3d131d..5b1dabb1a0 100644
--- a/src/soc/intel/alderlake/chip.h
+++ b/src/soc/intel/alderlake/chip.h
@@ -799,6 +799,15 @@ struct soc_intel_alderlake_config {
 		PD_TIER_PREMIUM = 25000,
 		PD_TIER_VOLUME  = 27000
 	} vccin_aux_imon_iccmax;
+
+	/* Enable / Disable(default) Type C Port x Convert to TypeA */
+	bool enabletcsscovtypea[4];
+
+	/*
+	 * PCH xhci port x for Type C Port x mapping.
+	 * Input PCH xhci port x for Type C Port 0 mapping.
+	 */
+	uint8_t mappingpchxhciusba[4];
 };
 
 typedef struct soc_intel_alderlake_config config_t;
diff --git a/src/soc/intel/alderlake/fsp_params.c b/src/soc/intel/alderlake/fsp_params.c
index d9204b4097..0de9fe4f66 100644
--- a/src/soc/intel/alderlake/fsp_params.c
+++ b/src/soc/intel/alderlake/fsp_params.c
@@ -650,6 +650,13 @@ static void fill_fsps_tcss_params(FSP_S_CONFIG *s_cfg,
 			s_cfg->UsbTcPortEn |= BIT(i);
 	}
 
+	for (int i = 0; i < MAX_TYPE_C_PORTS; i++) {
+		if (config->enabletcsscovtypea[i]) {
+			s_cfg->EnableTcssCovTypeA[i] = config->enabletcsscovtypea[i];
+			s_cfg->MappingPchXhciUsbA[i] = config->mappingpchxhciusba[i];
+		}
+	}
+
 	s_cfg->Usb4CmMode = CONFIG(SOFTWARE_CONNECTION_MANAGER);
 }