From 195924d6acb2ad21fe51920bb4b796ae0ce25567 Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Jonathan=20Neusch=C3=A4fer?= <j.neuschaefer@gmx.net>
Date: Thu, 11 Aug 2016 22:49:14 +0200
Subject: [PATCH] UPSTREAM: soc/ucb/riscv: select BOOTBLOCK_CONSOLE

BUG=None
BRANCH=None
TEST=None

Signed-off-by: Jonathan Neuschfer <j.neuschaefer@gmx.net>
Reviewed-on: https://review.coreboot.org/16158
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

Change-Id: I847d7686dec04e9fae7db13d53adc8ca32c56f3a
Reviewed-on: https://chromium-review.googlesource.com/370705
Commit-Ready: Furquan Shaikh <furquan@chromium.org>
Tested-by: Furquan Shaikh <furquan@chromium.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
---
 src/soc/ucb/riscv/Kconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/src/soc/ucb/riscv/Kconfig b/src/soc/ucb/riscv/Kconfig
index 744edffa1b..ff50f6f835 100644
--- a/src/soc/ucb/riscv/Kconfig
+++ b/src/soc/ucb/riscv/Kconfig
@@ -4,6 +4,7 @@ config SOC_UCB_RISCV
 	select ARCH_VERSTAGE_RISCV
 	select ARCH_ROMSTAGE_RISCV
 	select ARCH_RAMSTAGE_RISCV
+	select BOOTBLOCK_CONSOLE
 	bool
 	default n