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rk3288: Fix SPI clock divisor calculation

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The code to calculate the RK3288 SPI controller's internal clock divisor
is wrong: it assumes that the divisor register was an "n-1" divisor when
it actually isn't (due to some misleading kernel code that was copied in
here). This means that all SPI clocks are currently running lower than
expected.

This patch fixes the calculation and changes all callers such that the
effective speeds stay the same.

BRANCH=veyron
BUG=chrome-os-partner:38352
TEST=Booted Jerry with and without the patch, dumping the divisor for
flash and EC clocks. Made sure it stays the same.

Change-Id: I094d57a5933c8b849f5c66194e6cc2952ab68b90
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/262269
Reviewed-by: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 1fd5b990f937019a9bee7bd693c91d6e2fca1adb)
jwerner: Added Gus, Jaq and Minnie, removed Danger and Rialto. Replaced
	 write32() with writel().
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/262805
This commit is contained in:
Julius Werner 2015-03-24 16:12:08 -07:00 • committed by ChromeOS Commit Bot
commit 1900fe4437
9 changed files with 17 additions and 21 deletions
Download patch file Download diff file Expand all files Collapse all files

2
src/mainboard/google/veyron_brain/bootblock.c
View file

@ -70,7 +70,7 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
setup_chromeos_gpios();
}

4
src/mainboard/google/veyron_gus/bootblock.c
View file

@ -68,11 +68,11 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
/* spi0 for chrome ec */
writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
setup_chromeos_gpios();
}

4
src/mainboard/google/veyron_jaq/bootblock.c
View file

@ -68,11 +68,11 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
/* spi0 for chrome ec */
writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
setup_chromeos_gpios();
}

4
src/mainboard/google/veyron_jerry/bootblock.c
View file

@ -68,11 +68,11 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
/* spi0 for chrome ec */
writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
setup_chromeos_gpios();
}

4
src/mainboard/google/veyron_mighty/bootblock.c
View file

@ -68,11 +68,11 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
/* spi0 for chrome ec */
writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
setup_chromeos_gpios();
}

4
src/mainboard/google/veyron_minnie/bootblock.c
View file

@ -68,11 +68,11 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
/* spi0 for chrome ec */
writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
setup_chromeos_gpios();
}

4
src/mainboard/google/veyron_pinky/bootblock.c
View file

@ -68,11 +68,11 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
/* spi0 for chrome ec */
writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
setup_chromeos_gpios();
}

4
src/mainboard/google/veyron_speedy/bootblock.c
View file

@ -68,11 +68,11 @@ void bootblock_mainboard_init(void)
/* spi2 for firmware ROM */
writel(IOMUX_SPI2_CSCLK, &rk3288_grf->iomux_spi2csclk);
writel(IOMUX_SPI2_TXRX, &rk3288_grf->iomux_spi2txrx);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 11*MHz);
rockchip_spi_init(CONFIG_BOOT_MEDIA_SPI_BUS, 9900*KHz);
/* spi0 for chrome ec */
writel(IOMUX_SPI0, &rk3288_grf->iomux_spi0);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 9*MHz);
rockchip_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, 8250*KHz);
setup_chromeos_gpios();
}

8
src/soc/rockchip/rk3288/spi.c
View file

@ -94,12 +94,8 @@ static void rockchip_spi_enable_chip(struct rockchip_spi *regs, int enable)
static void rockchip_spi_set_clk(struct rockchip_spi *regs, unsigned int hz)
{
unsigned short clk_div = 0;
/* Calculate clock divisor. */
clk_div = SPI_SRCCLK_HZ / hz;
clk_div = (clk_div + 1) & 0xfffe;
assert((clk_div - 1) * hz == SPI_SRCCLK_HZ);
unsigned short clk_div = SPI_SRCCLK_HZ / hz;
assert(clk_div * hz == SPI_SRCCLK_HZ && !(clk_div & 1));
writel(clk_div, &regs->baudr);
}