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veyron: add ELPIDA F8132A3MA and FA232A2MA sdram

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BRANCH=None
TEST=Boot from veyron
BUG=None

Change-Id: I725cfb04ff46f7e6493e0e12a464c45b1362bc1a
Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/261083
Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 0ddd03f8757b5122f6ca87baffdf95c46e356e53)
jwerner: added Jaq, Gus and Minnie, removed Danger
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/261580
This commit is contained in:
jinkun.hong 2015-03-19 14:51:56 +08:00 • committed by ChromeOS Commit Bot
commit b2f35bc5d9
24 changed files with 1264 additions and 16 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/mainboard/google/veyron_brain/sdram_configs.c
View file

@ -32,11 +32,11 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */

78
src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-elpida-2GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* two ELPIDA F8132A3MA-GD-F chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 2,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0
},

78
src/mainboard/google/veyron_brain/sdram_inf/sdram-lpddr3-elpida-4GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* two ELPIDA FA232A2MA-GC-F chips */
{
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 6,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0
},

4
src/mainboard/google/veyron_gus/sdram_configs.c
View file

@ -32,11 +32,11 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */

78
src/mainboard/google/veyron_gus/sdram_inf/sdram-lpddr3-elpida-2GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* two ELPIDA F8132A3MA-GD-F chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 2,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0
},

78
src/mainboard/google/veyron_gus/sdram_inf/sdram-lpddr3-elpida-4GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* two ELPIDA FA232A2MA-GC-F chips */
{
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 6,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0
},

4
src/mainboard/google/veyron_jaq/sdram_configs.c
View file

@ -32,11 +32,11 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */

78
src/mainboard/google/veyron_jaq/sdram_inf/sdram-lpddr3-elpida-2GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* two ELPIDA F8132A3MA-GD-F chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 2,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0
},

78
src/mainboard/google/veyron_jaq/sdram_inf/sdram-lpddr3-elpida-4GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* two ELPIDA FA232A2MA-GC-F chips */
{
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 6,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0
},

4
src/mainboard/google/veyron_jerry/sdram_configs.c
View file

@ -32,11 +32,11 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */

78
src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-2GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* two ELPIDA F8132A3MA-GD-F chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 2,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0
},

78
src/mainboard/google/veyron_jerry/sdram_inf/sdram-lpddr3-elpida-4GB.inc Normal file
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@ -0,0 +1,78 @@
{
/* two ELPIDA FA232A2MA-GC-F chips */
{
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 6,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0
},

4
src/mainboard/google/veyron_mighty/sdram_configs.c
View file

@ -32,11 +32,11 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */

78
src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-2GB.inc Normal file
View file

@ -0,0 +1,78 @@
{
/* two ELPIDA F8132A3MA-GD-F chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 2,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0
},

78
src/mainboard/google/veyron_mighty/sdram_inf/sdram-lpddr3-elpida-4GB.inc Normal file
View file

@ -0,0 +1,78 @@
{
/* two ELPIDA FA232A2MA-GC-F chips */
{
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 6,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0
},

4
src/mainboard/google/veyron_minnie/sdram_configs.c
View file

@ -32,11 +32,11 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */

78
src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-2GB.inc Normal file
View file

@ -0,0 +1,78 @@
{
/* two ELPIDA F8132A3MA-GD-F chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 2,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0
},

78
src/mainboard/google/veyron_minnie/sdram_inf/sdram-lpddr3-elpida-4GB.inc Normal file
View file

@ -0,0 +1,78 @@
{
/* two ELPIDA FA232A2MA-GC-F chips */
{
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 6,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0
},

4
src/mainboard/google/veyron_pinky/sdram_configs.c
View file

@ -32,11 +32,11 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */

78
src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-2GB.inc Normal file
View file

@ -0,0 +1,78 @@
{
/* two ELPIDA F8132A3MA-GD-F chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 2,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0
},

78
src/mainboard/google/veyron_pinky/sdram_inf/sdram-lpddr3-elpida-4GB.inc Normal file
View file

@ -0,0 +1,78 @@
{
/* two ELPIDA FA232A2MA-GC-F chips */
{
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 6,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0
},

4
src/mainboard/google/veyron_speedy/sdram_configs.c
View file

@ -32,11 +32,11 @@ static struct rk3288_sdram_params sdram_configs[] = {
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 0101 */
#include "sdram_inf/sdram-ddr3-samsung-2GB.inc" /* ram_code = 0110 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-elpida-2GB.inc" /* ram_code = 0111 */
#include "sdram_inf/sdram-lpddr3-samsung-4GB.inc" /* ram_code = 1000 */
#include "sdram_inf/sdram-lpddr3-hynix-4GB.inc" /* ram_code = 1001 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1010 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-lpddr3-elpida-4GB.inc" /* ram_code = 1011 */
#include "sdram_inf/sdram-unused.inc" /* ram_code = 1100 */
#include "sdram_inf/sdram-ddr3-hynix-2GB.inc" /* ram_code = 1101 */
#include "sdram_inf/sdram-ddr3-samsung-4GB.inc" /* ram_code = 1110 */

78
src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-2GB.inc Normal file
View file

@ -0,0 +1,78 @@
{
/* two ELPIDA F8132A3MA-GD-F chips */
{
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xA,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 2,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 9,
.odt = 0
},

78
src/mainboard/google/veyron_speedy/sdram_inf/sdram-lpddr3-elpida-4GB.inc Normal file
View file

@ -0,0 +1,78 @@
{
/* two ELPIDA FA232A2MA-GC-F chips */
{
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
},
{
.rank = 0x2,
.col = 0xB,
.bk = 0x3,
.bw = 0x2,
.dbw = 0x2,
.row_3_4 = 0x0,
.cs0_row = 0xE,
.cs1_row = 0xE
}
},
{
.togcnt1u = 0x215,
.tinit = 0xC8,
.trsth = 0x0,
.togcnt100n = 0x35,
.trefi = 0x26,
.tmrd = 0x2,
.trfc = 0x70,
.trp = 0x2000D,
.trtw = 0x6,
.tal = 0x0,
.tcl = 0x8,
.tcwl = 0x4,
.tras = 0x17,
.trc = 0x24,
.trcd = 0xD,
.trrd = 0x6,
.trtp = 0x4,
.twr = 0x8,
.twtr = 0x4,
.texsr = 0x76,
.txp = 0x4,
.txpdll = 0x0,
.tzqcs = 0x30,
.tzqcsi = 0x0,
.tdqs = 0x1,
.tcksre = 0x2,
.tcksrx = 0x2,
.tcke = 0x4,
.tmod = 0x0,
.trstl = 0x0,
.tzqcl = 0xC0,
.tmrr = 0x4,
.tckesr = 0x8,
.tdpd = 0x1F4
},
{
.dtpr0 = 0x48D7DD93,
.dtpr1 = 0x187008D8,
.dtpr2 = 0x121076,
.mr[0] = 0x0,
.mr[1] = 0xC3,
.mr[2] = 0x6,
.mr[3] = 0x1
},
.noc_timing = 0x20D266A4,
.noc_activate = 0x5B6,
.ddrconfig = 6,
.ddr_freq = 533*MHz,
.dramtype = LPDDR3,
.num_channels = 2,
.stride = 13,
.odt = 0
},