From 188cd88ac7d6f7af4b0a2ca832e096c1e9d8bf6f Mon Sep 17 00:00:00 2001 From: Payne Lin Date: Fri, 19 Dec 2025 15:38:38 +0800 Subject: [PATCH] soc/mediatek/mt8196: Correct MIPI register control Configuring pll_con1 is wrong. Change it to voltage_sel. BUG=b:424782827 TEST=Build pass, boot ok. Verify display output on the following platforms: - 8196 Navi: eDP path. - 8189 Skywalker: eDP path. - 8189 Padme: single MIPI path (without DSC). - 8196 Sapphire: dual MIPI path (with DSC). Change-Id: I300af87f3b7850cb994bc01c0572279ba18efac0 Signed-off-by: Payne Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/90557 Reviewed-by: Yu-Ping Wu Reviewed-by: Chen-Tsung Hsieh Reviewed-by: Yidi Lin Tested-by: build bot (Jenkins) --- src/soc/mediatek/mt8196/dsi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/mediatek/mt8196/dsi.c b/src/soc/mediatek/mt8196/dsi.c index 6d6705986b..0ea12b2931 100644 --- a/src/soc/mediatek/mt8196/dsi.c +++ b/src/soc/mediatek/mt8196/dsi.c @@ -19,10 +19,10 @@ void mtk_dsi_configure_mipi_tx(struct mipi_tx_regs *mipi_tx_reg, u32 data_rate, /* Select different voltage when different data rate */ if (data_rate < (u32)2500 * MHz) { - clrsetbits32(&mipi_tx_reg->pll_con1, RG_DSI_PRD_REF_SEL, RG_DSI_PRD_REF_MINI); + clrsetbits32(&mipi_tx_reg->voltage_sel, RG_DSI_PRD_REF_SEL, RG_DSI_PRD_REF_MINI); write32(&mipi_tx_reg->cdphy_preserved, 0xFFFF00F0); } else { - clrsetbits32(&mipi_tx_reg->pll_con1, RG_DSI_PRD_REF_SEL, RG_DSI_PRD_REF_DEF); + clrsetbits32(&mipi_tx_reg->voltage_sel, RG_DSI_PRD_REF_SEL, RG_DSI_PRD_REF_DEF); write32(&mipi_tx_reg->cdphy_preserved, 0xFFFF0030); }