From 1777f962fd8efc2f6afc6e81fd52db7dbbba56aa Mon Sep 17 00:00:00 2001 From: "lai.kaiden" Date: Tue, 3 Feb 2026 14:03:34 +0800 Subject: [PATCH] mb/google/ocelot/var/ocicat: Remove RTD3 config for SSD The ocicat hardware design does not have a power load switch for the SSD , so remove the RTD3 chip driver and its associated GPIO configurations (enable/reset) in the overridetree. BUG=b:481143310 TEST=Build and boot to OS,verify SSD still functions correctly and power state transitions align with HW design. Change-Id: Iace755963109caa07db036cb7b2fce88eb246d2c Signed-off-by: lai.kaiden Reviewed-on: https://review.coreboot.org/c/coreboot/+/91070 Tested-by: build bot (Jenkins) Reviewed-by: Pranava Y N --- .../google/ocelot/variants/ocicat/overridetree.cb | 7 ------- 1 file changed, 7 deletions(-) diff --git a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb index 61a9c72b96..8ed23a7148 100644 --- a/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb +++ b/src/mainboard/google/ocelot/variants/ocicat/overridetree.cb @@ -365,13 +365,6 @@ chip soc/intel/pantherlake .clk_req = 3, .flags = PCIE_RP_CLK_REQ_DETECT | PCIE_RP_LTR | PCIE_RP_AER, }" - chip soc/intel/common/block/pcie/rtd3 - register "is_storage" = "true" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_H18)" - register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A08)" - register "srcclk_pin" = "3" - device generic 0 on end - end end # Gen4 M.2 SSD device ref pcie_rp5 on