From 16062b582a7e4ea405eb58a9df8cfe5279b2684b Mon Sep 17 00:00:00 2001 From: Jamie Ryu Date: Mon, 21 Oct 2024 11:20:40 -0700 Subject: [PATCH] soc/intel/pantherlake: Update PlatformDebugOption to Trace Ready This enables SOC_INTEL_DEBUG_CONSENT to set PlatformDebugOption to Trace Ready to have the safe configurations for Panther Lake ES SoC. This safe configuration will be removed once the feature is fully verified and safe to be set to the default value. BUG=b:373915085 TEST=Build fatcat and check the platform boots without an issue. Change-Id: I1eaabcb2e2aaff16ee4e64d1c7709b229de18459 Signed-off-by: Jamie Ryu Reviewed-on: https://review.coreboot.org/c/coreboot/+/84823 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) Reviewed-by: Pranava Y N --- src/soc/intel/pantherlake/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 9d17cb2050..76a84cdeb8 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -94,6 +94,7 @@ config SOC_INTEL_PANTHERLAKE_BASE select SOC_INTEL_CSE_LITE_PSR if MAINBOARD_HAS_CHROMEOS && SOC_INTEL_CSE_LITE_SKU select SOC_INTEL_CSE_SEND_EOP_LATE if !MAINBOARD_HAS_CHROMEOS select SOC_INTEL_CSE_SET_EOP + select SOC_INTEL_DEBUG_CONSENT # TODO: Remove the safe setting for ES SoC select SOC_INTEL_GFX_NON_PREFETCHABLE_MMIO select SOC_INTEL_IOE_DIE_SUPPORT select SOC_INTEL_MEM_MAPPED_PM_CONFIGURATION