From 15b903e1fd1219f357d37ce3b10c5170c8775811 Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Wed, 24 Sep 2025 11:23:31 -0700 Subject: [PATCH] soc/intel/pantherlake: Add DDR5 memory type debug message MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This commit introduces a debug message to the DDR5 memory type initialization process within the Panther Lake SoC. By adding this log, developers can gain better insights when diagnosing issues related to DDR5 memory configurations. BUG=none TEST=Verify the debug message is displayed during DDR5 initialization. Change-Id: I77ceea0f7a29983dd2e4ad1af26a0383721d7ca0 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/89331 Reviewed-by: Wonkyu Kim Reviewed-by: Jérémy Compostella Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/pantherlake/meminit.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/intel/pantherlake/meminit.c b/src/soc/intel/pantherlake/meminit.c index 8d1a933992..01c217be3d 100644 --- a/src/soc/intel/pantherlake/meminit.c +++ b/src/soc/intel/pantherlake/meminit.c @@ -196,6 +196,7 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, switch (mb_cfg->type) { case MEM_TYPE_DDR5: + printk(BIOS_DEBUG, "%s: module type is DDR5\n", __func__); meminit_ddr(mem_cfg, &mb_cfg->ddr_config); dq_dqs_auto_detect = true; /*