From 14b51ea7376d169135528e6514b2c31a6e4b9edf Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Fri, 5 Sep 2014 09:06:55 -0500 Subject: [PATCH] tegra132: fix host1x clock selection The host1x clock selection register has a different encoding than the major of other clock source registers. This results in PLLM_OUT0 being selected when PLLP_OUT0 was requested. Use the clock_configure_irregular_source() method to correct this situation. BUG=chrome-os-partner:31820 BRANCH=None TEST=Noted proper clock selection was achieved. Change-Id: Idc1ea88e2e1f2abc0c13e7aa1e8bdfa981da388e Signed-off-by: Aaron Durbin Reviewed-on: https://chromium-review.googlesource.com/216422 Reviewed-by: Furquan Shaikh Reviewed-by: Tom Warren --- src/soc/nvidia/tegra132/i2c6.c | 8 +++++--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/src/soc/nvidia/tegra132/i2c6.c b/src/soc/nvidia/tegra132/i2c6.c index 4efba23ea7..644c89ddb3 100644 --- a/src/soc/nvidia/tegra132/i2c6.c +++ b/src/soc/nvidia/tegra132/i2c6.c @@ -26,7 +26,6 @@ #include #include "delay.h" -#define I2C6_BUS 5 #define I2C6_PADCTL 0xC001 #define DPAUX_HYBRID_PADCTL 0x545C0124 @@ -90,8 +89,11 @@ void soc_configure_i2c6pad(void) remove_clamps(POWER_PARTID_SOR); unreset_sor_periphs(); - /* Host1X needs a valid clock source so DPAUX can be accessed */ - clock_configure_source(host1x, PLLP, 204000); + /* + * Host1X needs a valid clock source so DPAUX can be accessed. Note that + * 4 is the PLLP_OUT0 source for this register. + */ + clock_configure_irregular_source(host1x, PLLP, 204000, 4); /* Now we can write the I2C6 mux in DPAUX */ write32(I2C6_PADCTL, (void *)DPAUX_HYBRID_PADCTL);