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soc/intel/common/block: Include register offsets for POWER_CTL

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Details:
- Add (POWER_CTL) – Offset 0x1fc required bits.

Change-Id: Ief7f514c5837cb2f7c3158b67c4f6fed86796e71
Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84178
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
This commit is contained in:
Saurabh Mishra 2024-09-02 13:39:55 +05:30 • committed by Subrata Banik
commit 174755f555
1 changed files with 3 additions and 0 deletions
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3
src/soc/intel/common/block/include/intelblocks/msr.h
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@ -50,7 +50,10 @@
#define PRMRR_PHYS_MASK_VALID (1 << 11)
#define MSR_PRMRR_VALID_CONFIG 0x1fb
#define MSR_POWER_CTL 0x1fc
#define ENABLE_BIDIR_PROCHOT (1 << 0)
#define POWER_CTL_C1E_MASK (1 << 1)
#define PWR_PERF_PLATFORM_OVR (1 << 18)
#define VR_THERM_ALERT_DISABLE_LOCK (1 << 23)
#define MSR_PRMRR_BASE_0 0x2a0
#define MSR_EVICT_CTL 0x2e0
#define MSR_LT_CONTROL 0x2e7