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broadwell: Increase I2C SDA hold timing to 300ns

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I2C bus SDA hold time can be marginal with 60ns value, especially
when there is level shifter on the bus. So program it to 300ns
based on Fast-mode specification, which is between 0 to 900ns.
Apply the same timing for Standard-mode as well.

Refer to original bug on BayTrail chrome-os-partner:28092, this
is to carry forward the fix to Broadwell.

BRANCH=chromeos-2013.04
BUG=chrome-os-partner:33378
TEST=suspend resume test, watch for I2C errors

Change-Id: I93200b141602163903f5c9f52b94013bcf3382a5
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 72b82a1d5d
Original-Change-Id: I995d6868a44f2578a6d0b18dd5e8548f3c3cd494
Original-Signed-off-by: Chiranjeevi Rapolu <chiranjeevi.rapolu@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/226386
Original-Reviewed-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9467
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Chiranjeevi Rapolu 2014-10-29 17:26:05 -07:00 • committed by Stefan Reinauer
commit 1164d51828
1 changed files with 4 additions and 4 deletions
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8
src/soc/intel/broadwell/acpi/serialio.asl
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@ -205,8 +205,8 @@ Device (I2C0)
Name (_UID, 1)
Name (_ADR, 0x00150001)
Name (SSCN, Package () { 432, 507, 9 })
Name (FMCN, Package () { 72, 160, 9 })
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
// BAR0 is assigned during PCI enumeration and saved into NVS
Name (RBUF, ResourceTemplate ()
@ -276,8 +276,8 @@ Device (I2C1)
Name (_UID, 1)
Name (_ADR, 0x00150002)
Name (SSCN, Package () { 432, 507, 9 })
Name (FMCN, Package () { 72, 160, 9 })
Name (SSCN, Package () { 432, 507, 30 })
Name (FMCN, Package () { 72, 160, 30 })
// BAR0 is assigned during PCI enumeration and saved into NVS
Name (RBUF, ResourceTemplate ()