From 105598545e4bfab6d53b3d2d1cc21b1281a5e1ab Mon Sep 17 00:00:00 2001 From: Bora Guvendik Date: Thu, 23 Oct 2025 13:30:39 -0700 Subject: [PATCH] soc/intel/pantherlake: Update thermal design current parameters MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Update thermal design current (TDC) values for GT domain across multiple PTL SKUs based on input from Power and Performance team. BUG=none TEST=Boot to OS on fatcat device and check performance. Change-Id: I6333f8b5db8c7fc1739d0772d83bfe602a837a53 Signed-off-by: Bora Guvendik Reviewed-on: https://review.coreboot.org/c/coreboot/+/89697 Reviewed-by: Wonkyu Kim Reviewed-by: Jérémy Compostella Reviewed-by: Ma, Zhixing Tested-by: build bot (Jenkins) --- src/soc/intel/pantherlake/chipset_ptl.cb | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/src/soc/intel/pantherlake/chipset_ptl.cb b/src/soc/intel/pantherlake/chipset_ptl.cb index 1c6075aff9..676a309f2e 100644 --- a/src/soc/intel/pantherlake/chipset_ptl.cb +++ b/src/soc/intel/pantherlake/chipset_ptl.cb @@ -10,7 +10,7 @@ chip soc/intel/pantherlake }" register "thermal_design_current[PTL_SKU_1]" = "{ [VR_DOMAIN_IA] = 23 * 8, - [VR_DOMAIN_GT] = 15 * 8 + [VR_DOMAIN_GT] = 23 * 8 }" register "icc_max[PTL_SKU_1]" = "{ [VR_DOMAIN_IA] = 80 * 4, @@ -27,7 +27,7 @@ chip soc/intel/pantherlake }" register "thermal_design_current[PTL_SKU_5]" = "{ [VR_DOMAIN_IA] = 23 * 8, - [VR_DOMAIN_GT] = 15 * 8 + [VR_DOMAIN_GT] = 23 * 8 }" register "icc_max[PTL_SKU_5]" = "{ [VR_DOMAIN_IA] = 80 * 4, @@ -44,7 +44,7 @@ chip soc/intel/pantherlake }" register "thermal_design_current[PTL_SKU_2]" = "{ [VR_DOMAIN_IA] = 31 * 8, - [VR_DOMAIN_GT] = 25 * 8 + [VR_DOMAIN_GT] = 44 * 8 }" register "icc_max[PTL_SKU_2]" = "{ [VR_DOMAIN_IA] = 107 * 4, @@ -67,7 +67,7 @@ chip soc/intel/pantherlake register "thermal_design_current[PTL_SKU_6]" = "{ [VR_DOMAIN_IA] = 31 * 8, - [VR_DOMAIN_GT] = 25 * 8 + [VR_DOMAIN_GT] = 44 * 8 }" register "icc_max[PTL_SKU_6]" = "{ [VR_DOMAIN_IA] = 90 * 4, @@ -77,7 +77,6 @@ chip soc/intel/pantherlake }" register "tdc_mode[VR_DOMAIN_IA]" = "TDC_IRMS" - register "tdc_mode[VR_DOMAIN_GT]" = "TDC_IRMS" register "tdc_time_window_ms[VR_DOMAIN_IA]" = "28000" # Set the power state thresholds according to document 813278