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UPSTREAM: inteltool: Add Skylake PCI id in memory.c

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BUG=none
BRANCH=none
TEST=none

Change-Id: I0b3a475c1c875e51929e981d7a809f5e40b00e43
Signed-off-by: Patrick Georgi <pgeorgi@google.com>
Original-Commit-Id: 21e7424fc9
Original-Change-Id: I751e887bd90a258a69d13ea4ee9a409c8c86a3c3
Original-Signed-off-by: Nico Huber <nico.huber@secunet.com>
Original-Reviewed-on: https://review.coreboot.org/19591
Original-Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Original-Reviewed-by: Philippe Mathieu-Daud <philippe.mathieu.daude@gmail.com>
Original-Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-on: https://chromium-review.googlesource.com/531189
Commit-Ready: Patrick Georgi <pgeorgi@chromium.org>
Tested-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-by: Patrick Georgi <pgeorgi@chromium.org>
This commit is contained in:
Nico Huber 2017-04-24 15:06:09 +02:00 • committed by chrome-bot
commit 1013d9cb9a
1 changed files with 1 additions and 0 deletions
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util/inteltool/memory.c
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@ -218,6 +218,7 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc, const char *dump_s
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_E3:
case PCI_DEVICE_ID_INTEL_CORE_4TH_GEN_U:
case PCI_DEVICE_ID_INTEL_CORE_5TH_GEN_U:
case PCI_DEVICE_ID_INTEL_CORE_6TH_GEN_WST:
mchbar_phys = pci_read_long(nb, 0x48);
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */