From 0fabdbb05826160beb8ee8f89339b18a49e87ab8 Mon Sep 17 00:00:00 2001 From: Furquan Shaikh Date: Mon, 3 Nov 2014 14:39:11 -0800 Subject: [PATCH] rk3288: Use timestamp region for pre-cbmem timestamps BUG=None BRANCH=None TEST=Compiles successfully for veyron_pinky Change-Id: I3862e9bf2c32085c921adae4c1dcdf88ff0f3ff3 Signed-off-by: Furquan Shaikh Reviewed-on: https://chromium-review.googlesource.com/227243 Reviewed-by: Aaron Durbin Commit-Queue: Furquan Shaikh Tested-by: Furquan Shaikh --- configs/config.veyron_pinky | 1 - src/mainboard/google/veyron_jerry/romstage.c | 27 ++++------------ src/mainboard/google/veyron_pinky/romstage.c | 32 ++++++------------- src/soc/rockchip/rk3288/Kconfig | 2 ++ src/soc/rockchip/rk3288/bootblock.c | 3 ++ .../rockchip/rk3288/include/soc/memlayout.ld | 3 +- 6 files changed, 22 insertions(+), 46 deletions(-) diff --git a/configs/config.veyron_pinky b/configs/config.veyron_pinky index 8cb7f69251..7192c3bcac 100644 --- a/configs/config.veyron_pinky +++ b/configs/config.veyron_pinky @@ -2,7 +2,6 @@ CONFIG_VENDOR_GOOGLE=y CONFIG_BOARD_GOOGLE_VEYRON_PINKY=y CONFIG_COREBOOT_ROMSIZE_KB_1024=y # CONFIG_CONSOLE_SERIAL is not set -CONFIG_COLLECT_TIMESTAMPS=y # CONFIG_ELOG=y # CONFIG_CONSOLE_CBMEM=y CONFIG_FLASHMAP_OFFSET=0x00100000 diff --git a/src/mainboard/google/veyron_jerry/romstage.c b/src/mainboard/google/veyron_jerry/romstage.c index 94a65a5037..8294aef0e6 100644 --- a/src/mainboard/google/veyron_jerry/romstage.c +++ b/src/mainboard/google/veyron_jerry/romstage.c @@ -79,13 +79,8 @@ static void configure_l2ctlr(void) void main(void) { void *entry; -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -93,13 +88,9 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + timestamp_add_now(TS_BEFORE_INITRAM); sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -108,20 +99,14 @@ void main(void) _dma_coherent_size/MiB, DCACHE_OFF); cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); -#endif entry = vboot2_load_ramstage(); if (entry == NULL) { - timestamp_add(TS_START_COPYRAM, timestamp_get()); + timestamp_add_now(TS_START_COPYRAM); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/ramstage"); - timestamp_add(TS_END_COPYRAM, timestamp_get()); + timestamp_add_now(TS_END_COPYRAM); if (entry == (void *)-1) die("failed to load ramstage\n"); } diff --git a/src/mainboard/google/veyron_pinky/romstage.c b/src/mainboard/google/veyron_pinky/romstage.c index 94a65a5037..58e8a53491 100644 --- a/src/mainboard/google/veyron_pinky/romstage.c +++ b/src/mainboard/google/veyron_pinky/romstage.c @@ -79,13 +79,8 @@ static void configure_l2ctlr(void) void main(void) { void *entry; -#if CONFIG_COLLECT_TIMESTAMPS - uint64_t start_romstage_time; - uint64_t before_dram_time; - uint64_t after_dram_time; - uint64_t base_time = timestamp_get(); - start_romstage_time = timestamp_get(); -#endif + + timestamp_add_now(TS_START_ROMSTAGE); console_init(); configure_l2ctlr(); @@ -93,13 +88,10 @@ void main(void) /* vdd_log 1200mv is enough for ddr run 666Mhz */ regulate_vdd_log(1200); -#if CONFIG_COLLECT_TIMESTAMPS - before_dram_time = timestamp_get(); -#endif + + timestamp_add_now(TS_BEFORE_INITRAM); sdram_init(get_sdram_config()); -#if CONFIG_COLLECT_TIMESTAMPS - after_dram_time = timestamp_get(); -#endif + timestamp_add_now(TS_AFTER_INITRAM); /* Now that DRAM is up, add mappings for it and DMA coherency buffer. */ mmu_config_range((uintptr_t)_dram/MiB, @@ -108,25 +100,19 @@ void main(void) _dma_coherent_size/MiB, DCACHE_OFF); cbmem_initialize_empty(); -#if CONFIG_COLLECT_TIMESTAMPS - timestamp_init(base_time); - timestamp_add(TS_START_ROMSTAGE, start_romstage_time); - timestamp_add(TS_BEFORE_INITRAM, before_dram_time); - timestamp_add(TS_AFTER_INITRAM, after_dram_time); -#endif entry = vboot2_load_ramstage(); if (entry == NULL) { - timestamp_add(TS_START_COPYRAM, timestamp_get()); + timestamp_add_now(TS_START_COPYRAM); entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, CONFIG_CBFS_PREFIX "/ramstage"); - timestamp_add(TS_END_COPYRAM, timestamp_get()); + timestamp_add_now(TS_END_COPYRAM); if (entry == (void *)-1) die("failed to load ramstage\n"); } -#if CONFIG_COLLECT_TIMESTAMPS + timestamp_add_now(TS_END_ROMSTAGE); -#endif + stage_exit(entry); } diff --git a/src/soc/rockchip/rk3288/Kconfig b/src/soc/rockchip/rk3288/Kconfig index db07753a54..113f5e0cc3 100644 --- a/src/soc/rockchip/rk3288/Kconfig +++ b/src/soc/rockchip/rk3288/Kconfig @@ -32,6 +32,8 @@ config SOC_ROCKCHIP_RK3288 select ARCH_RAMSTAGE_ARM_V7 select HAVE_UART_MEMORY_MAPPED select BOOTBLOCK_CONSOLE + select COLLECT_TIMESTAMPS + select HAS_PRECBMEM_TIMESTAMP_REGION if SOC_ROCKCHIP_RK3288 diff --git a/src/soc/rockchip/rk3288/bootblock.c b/src/soc/rockchip/rk3288/bootblock.c index f2fe11cc38..8f6c92d0dc 100644 --- a/src/soc/rockchip/rk3288/bootblock.c +++ b/src/soc/rockchip/rk3288/bootblock.c @@ -26,11 +26,14 @@ #include #include #include +#include void bootblock_cpu_init(void) { rk3288_init_timer(); + timestamp_early_init(timestamp_get()); + if (IS_ENABLED(CONFIG_CONSOLE_SERIAL_UART)) { switch (CONFIG_CONSOLE_SERIAL_UART_ADDRESS) { case UART2_BASE: diff --git a/src/soc/rockchip/rk3288/include/soc/memlayout.ld b/src/soc/rockchip/rk3288/include/soc/memlayout.ld index 922e2f8784..dc002ff21d 100644 --- a/src/soc/rockchip/rk3288/include/soc/memlayout.ld +++ b/src/soc/rockchip/rk3288/include/soc/memlayout.ld @@ -39,7 +39,8 @@ SECTIONS VBOOT2_WORK(0xFF708000, 16K) OVERLAP_VERSTAGE_ROMSTAGE(0xFF70C000, 40K) PRERAM_CBFS_CACHE(0xFF716000, 4K) - STACK(0xFF717000, 4K) + STACK(0xFF717000, 3K) + TIMESTAMP(0xFF717C00, 1K) SRAM_END(0xFF718000) /* 4K of special SRAM in PMU power domain. Careful: only supports 32-bit