From 0f30eed3e810b34ce698f156bd5f2742a95d367b Mon Sep 17 00:00:00 2001 From: Angel Pons Date: Thu, 19 Mar 2026 09:45:49 +0100 Subject: [PATCH] Doc/nb/intel/haswell: Fix typo Chomeboxes ---> Chromeboxes Change-Id: Ifdd9a1374d4d021c2777694937da2c81d22004e7 Signed-off-by: Angel Pons Reviewed-on: https://review.coreboot.org/c/coreboot/+/91760 Reviewed-by: Matt DeVillier Tested-by: build bot (Jenkins) Reviewed-by: Alicja Michalska --- Documentation/northbridge/intel/haswell/mrc.bin.md | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/Documentation/northbridge/intel/haswell/mrc.bin.md b/Documentation/northbridge/intel/haswell/mrc.bin.md index 447d8fb391..2f31da377a 100644 --- a/Documentation/northbridge/intel/haswell/mrc.bin.md +++ b/Documentation/northbridge/intel/haswell/mrc.bin.md @@ -31,6 +31,6 @@ its location when building coreboot. When `mrc.bin` has finished executing, ECC is active on the channels populated with ECC DIMMs. However, `mrc.bin` was tailored specifically -for Haswell Chromebooks and Chomeboxes, none of which support ECC DRAM. +for Haswell Chromebooks and Chromeboxes, none of which support ECC DRAM. While ECC likely functions correctly, it is advised to further validate the correct operation of ECC if data integrity is absolutely critical.