From 0f0d5fc7252e42d585afa6b41f27d02539f2f071 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Tue, 29 Apr 2025 18:44:32 -0500 Subject: [PATCH] soc/intel/apollolake/acpi: Add function to get PCIe BAR Commit 12abfb43dc0a ("soc/intel/cnvi: Add CNVW OpRegion") added an ACPI function call to \_SB_.PCI0.GPCB(), which is present in the SoC common northbridge.asl, but not in the ApolloLake northbridge.asl. Add the missing GPCB function to the APL northbridge. Per Intel doc 336561, the PCIEXBAR starts at bit 28 vs 26 on other platforms. TEST=build/boot google/ampton, verify no ACPI errors in dmesg related to missing function/object, Windows boots without ACPI_BIOS_ERROR BSOD. Change-Id: Ib45d655a30bf68e9b3d24a444c505e515c4950a6 Signed-off-by: Matt DeVillier Reviewed-on: https://review.coreboot.org/c/coreboot/+/87486 Reviewed-by: Paul Menzel Reviewed-by: Sean Rhodes Tested-by: build bot (Jenkins) --- src/soc/intel/apollolake/acpi/northbridge.asl | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/soc/intel/apollolake/acpi/northbridge.asl b/src/soc/intel/apollolake/acpi/northbridge.asl index a304331f1d..fcbd1d0494 100644 --- a/src/soc/intel/apollolake/acpi/northbridge.asl +++ b/src/soc/intel/apollolake/acpi/northbridge.asl @@ -124,5 +124,12 @@ Device (PDRC) /* PCI Device Resource Consumption */ } } +/* Get PCIe BAR */ +Method (GPCB, 0, Serialized) +{ + Local0 = \_SB.PCI0.MCHC.PXBR << 28 + Return (Local0) +} + /* GFX 00:02.0 */ #include