From 0ef670a66a28212e29e543bc86d714f0ef8851ee Mon Sep 17 00:00:00 2001 From: Sowmya Aralguppe Date: Tue, 8 Jul 2025 10:47:41 +0530 Subject: [PATCH] mb/google/ocelot/var/ocelot: Configure FPS related changes This patch configures Interrupt, Enable and Reset pins for FPS. BUG=b:394208231 TEST=Build Ocelot and verify it compiles without any error. Change-Id: Ida4fab8da007403898e6843d5161249a5093fd54 Signed-off-by: Sowmya Aralguppe Reviewed-on: https://review.coreboot.org/c/coreboot/+/88351 Reviewed-by: Pranava Y N Tested-by: build bot (Jenkins) --- src/mainboard/google/ocelot/variants/ocelot/overridetree.cb | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb index 31959f5a27..56aa468b6e 100644 --- a/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb +++ b/src/mainboard/google/ocelot/variants/ocelot/overridetree.cb @@ -558,11 +558,11 @@ chip soc/intel/pantherlake register "hid" = "ACPI_DT_NAMESPACE_HID" register "uid" = "1" register "compat_string" = ""google,cros-ec-spi"" - register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_D01_IRQ)" - register "wake" = "GPE0_DW1_01" + register "irq" = "ACPI_IRQ_WAKE_LEVEL_LOW(GPP_E19_IRQ)" + register "wake" = "GPE0_DW1_19" register "has_power_resource" = "true" register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C15)" - register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E19)" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E05)" register "enable_delay_ms" = "3" device spi 0 on probe FP FP_PRESENT