diff --git a/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h b/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
index 76f165d061..47500defa3 100644
--- a/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/cezanne/soc_dmi_info.h
@@ -12,6 +12,7 @@
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    4   ///< DIMMs per channel in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
-#define SMBIOS_3_2_3_3_SUPPORT            1
+#define SMBIOS_3_2_SUPPORT                1
+#define SMBIOS_3_3_SUPPORT                1
 
 #endif /* SOC_DMI_INFO_H */
diff --git a/src/vendorcode/amd/fsp/common/dmi_info.h b/src/vendorcode/amd/fsp/common/dmi_info.h
index 5593d760f5..e38a44ed94 100644
--- a/src/vendorcode/amd/fsp/common/dmi_info.h
+++ b/src/vendorcode/amd/fsp/common/dmi_info.h
@@ -165,7 +165,7 @@ typedef struct {
   OUT UINT16                    MaximumVoltage;         ///< Maximum operating voltage for this device, in millivolts
   OUT UINT16                    ConfiguredVoltage;      ///< Configured voltage for this device, in millivolts
   // SMBIOS 3.2
-#ifdef SMBIOS_3_2_3_3_SUPPORT
+#ifdef SMBIOS_3_2_SUPPORT
   OUT UINT8                     MemoryTechnology;       ///< Memory technology type for this memory device
   OUT DMI_T17_MEMORY_OPERATING_MODE_CAPABILITY_VAR   MemoryOperatingModeCapability; ///< The operating modes supported by this memory device
   OUT CHAR8                     FirmwareVersion[10];    ///< String number for the firmware version of this memory device
@@ -178,9 +178,11 @@ typedef struct {
   OUT UINT64                    CacheSize;              ///< Size of the Cache portion of the memory device in Bytes, if any.
   OUT UINT64                    LogicalSize;            ///< Size of the Logical memory device in Bytes.
   // SMBIOS 3.3
+#ifdef SMBIOS_3_3_SUPPORT
   OUT UINT32                    ExtendedSpeed;          ///< Extended Speed
   OUT UINT32                    ExtendedConfiguredMemorySpeed; ///< Extended Configured memory speed
 #endif
+#endif
 } __packed TYPE17_DMI_INFO;
 
 /// Collection of pointers to the DMI records
diff --git a/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h b/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
index 3f24fe9b16..15c7b63a71 100644
--- a/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/glinda/soc_dmi_info.h
@@ -13,6 +13,7 @@
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    2   ///< DIMMs per channel in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_PART_NUMBER_SIZE     31
 
-#define SMBIOS_3_2_3_3_SUPPORT            1
+#define SMBIOS_3_2_SUPPORT                1
+#define SMBIOS_3_3_SUPPORT                1
 
 #endif /* SOC_DMI_INFO_H */
diff --git a/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h b/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
index 1c3cb1a0b1..bf35aea3e5 100644
--- a/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/mendocino/soc_dmi_info.h
@@ -12,6 +12,7 @@
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    2   ///< DIMMs per channel in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
-#define SMBIOS_3_2_3_3_SUPPORT            1
+#define SMBIOS_3_2_SUPPORT                1
+#define SMBIOS_3_3_SUPPORT                1
 
 #endif /* SOC_DMI_INFO_H */
diff --git a/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h b/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
index 1c3cb1a0b1..bf35aea3e5 100644
--- a/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/phoenix/soc_dmi_info.h
@@ -12,6 +12,7 @@
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    2   ///< DIMMs per channel in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_PART_NUMBER_SIZE     21
 
-#define SMBIOS_3_2_3_3_SUPPORT            1
+#define SMBIOS_3_2_SUPPORT                1
+#define SMBIOS_3_3_SUPPORT                1
 
 #endif /* SOC_DMI_INFO_H */
diff --git a/src/vendorcode/amd/fsp/renoir/soc_dmi_info.h b/src/vendorcode/amd/fsp/renoir/soc_dmi_info.h
index 5726dffa59..762320cdc3 100644
--- a/src/vendorcode/amd/fsp/renoir/soc_dmi_info.h
+++ b/src/vendorcode/amd/fsp/renoir/soc_dmi_info.h
@@ -12,6 +12,6 @@
 #define AGESA_STRUCT_DIMMS_PER_CHANNEL    4   ///< DIMMs per channel in AGESA FSP DMI T17 table
 #define AGESA_STRUCT_PART_NUMBER_SIZE     21 //TODO check
 
-#define SMBIOS_3_2_3_3_SUPPORT            1
+#define SMBIOS_3_2_SUPPORT                1
 
 #endif /* SOC_DMI_INFO_H */