From 0dbef76544f5bbaaf8e781faa45890477ed91ef0 Mon Sep 17 00:00:00 2001 From: Jason-jh Lin Date: Mon, 13 Jan 2025 00:26:14 +0800 Subject: [PATCH] soc/mediatek/mt8196: Add GCE ddren sel control to mminfra MMINFRA_GCE_DDREN_SEL is a setting for switching the DRAM transaction ACK from SPM: 0, non-SPM: 0x1. In MT8196, SPM has masked all the DDR requests, so this setting should be set to non-SPM whenever mminfra is powering on. Otherwise, GCE will hang when accessing DRAM. BUG=b:379039600 TEST=boot up ok, GCE can access DRAM continuously Change-Id: I30309b0426f803e28858eb15652a649927f94c7e Signed-off-by: Jason-jh Lin Reviewed-on: https://review.coreboot.org/c/coreboot/+/86027 Tested-by: build bot (Jenkins) Reviewed-by: Yu-Ping Wu Reviewed-by: Yidi Lin --- src/soc/mediatek/mt8196/include/soc/mminfra.h | 1 + src/soc/mediatek/mt8196/mminfra.c | 2 ++ 2 files changed, 3 insertions(+) diff --git a/src/soc/mediatek/mt8196/include/soc/mminfra.h b/src/soc/mediatek/mt8196/include/soc/mminfra.h index 13a4e5c376..4404040f2d 100644 --- a/src/soc/mediatek/mt8196/include/soc/mminfra.h +++ b/src/soc/mediatek/mt8196/include/soc/mminfra.h @@ -4,6 +4,7 @@ #define __SOC_MEDIATEK_MMINFRA_H__ /* mminfra_ao */ +#define MMINFRA_GCE_DDREN_SEL (MMINFRA_AO_CONFIG + 0x418) #define MMINFRA_GCE_PROT_EN (MMINFRA_AO_CONFIG + 0x428) /* mminfra0 */ diff --git a/src/soc/mediatek/mt8196/mminfra.c b/src/soc/mediatek/mt8196/mminfra.c index 55ddf47d30..c5eadf38ff 100644 --- a/src/soc/mediatek/mt8196/mminfra.c +++ b/src/soc/mediatek/mt8196/mminfra.c @@ -26,11 +26,13 @@ static void mm_gce_lock_prot_en(void) GCE_D_SLEEPPORT_RX_EN | GCE_D_HAND_SLEEPPORT_RX_EN | GCE_D_HAND_SLEEPPORT_TX_EN | GCE_M_SLEEPPORT_RX_EN | GCE_M_HAND_SLEEPPORT_RX_EN | GCE_M_HAND_SLEEPPORT_TX_EN); + write32p(MMINFRA_GCE_DDREN_SEL, 0); } static void mm_gce_release_prot_en(void) { write32p(MMINFRA_GCE_PROT_EN, 0); + write32p(MMINFRA_GCE_DDREN_SEL, 0x1); } static void mm_infra0_lock_prot_en(void)