soc/intel/pantherlake: Enable coreboot native logo rendering

This commit enables the `USE_COREBOOT_FOR_BMP_RENDERING` Kconfig option for
Panther Lake.

This allows the platform to utilize coreboot's native logo rendering
capabilities after the FSP initializes the display.

Additionally, this commit adds temporary MMIO definitions for the
Panther Lake I/O map: GMADR_BASE (0xB0000000) and GMADR_SIZE
(0x10000000). These definitions are necessary to program the IGD LMEM
BAR for accessible framebuffer and to enable Write Combine (WC) MTRR
caching for the LMEM BAR.

BUG=b:409718202
TEST=Built and booted google/fatcat. Verified boot splash was rendered
by coreboot as `USE_COREBOOT_FOR_BMP_RENDERING` was set to `y`.

Observed a slight delay (~10-30ms) in displaying BMP image with native
coreboot implementation compared to FSP-based rendering.

Change-Id: I658db63906e051fa82f3297f039f9e3c814df43f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/87542
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>

src/soc/intel/pantherlake/Kconfig

@@ -104,6 +104,7 @@ config SOC_INTEL_PANTHERLAKE_BASE
 	select TSC_MONOTONIC_TIMER
 	select UDELAY_TSC
 	select UDK_202302_BINDING
+	select USE_COREBOOT_FOR_BMP_RENDERING
 	select USE_X86_64_SUPPORT
 	select X86_INIT_NEED_1_SIPI
 	help

src/soc/intel/pantherlake/include/soc/iomap.h

@@ -86,6 +86,10 @@
 #define IOM_BASE_SIZE		0x10000
 #define IOM_BASE_ADDR_MAX	0x401080ffff /* ((IOM_BASE_ADDR + IOM_BASE_SIZE) - 1) */
 
+/* Temporary MMIO address for GMADR (aka LMEMBAR) with 256MB */
+#define GMADR_BASE		0xB0000000
+#define GMADR_SIZE		0x10000000
+
 /* I/O port address space */
 #define ACPI_BASE_ADDRESS	0x1800
 #define ACPI_BASE_SIZE		0x100