From 0ca46ac0d257f123fbc8c0d09f987b5dc0b9b9b0 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Mon, 5 May 2025 19:43:12 +0530 Subject: [PATCH] soc/intel/pantherlake: Enable coreboot native logo rendering This commit enables the `USE_COREBOOT_FOR_BMP_RENDERING` Kconfig option for Panther Lake. This allows the platform to utilize coreboot's native logo rendering capabilities after the FSP initializes the display. Additionally, this commit adds temporary MMIO definitions for the Panther Lake I/O map: GMADR_BASE (0xB0000000) and GMADR_SIZE (0x10000000). These definitions are necessary to program the IGD LMEM BAR for accessible framebuffer and to enable Write Combine (WC) MTRR caching for the LMEM BAR. BUG=b:409718202 TEST=Built and booted google/fatcat. Verified boot splash was rendered by coreboot as `USE_COREBOOT_FOR_BMP_RENDERING` was set to `y`. Observed a slight delay (~10-30ms) in displaying BMP image with native coreboot implementation compared to FSP-based rendering. Change-Id: I658db63906e051fa82f3297f039f9e3c814df43f Signed-off-by: Subrata Banik Reviewed-on: https://review.coreboot.org/c/coreboot/+/87542 Tested-by: build bot (Jenkins) Reviewed-by: Nick Vaccaro --- src/soc/intel/pantherlake/Kconfig | 1 + src/soc/intel/pantherlake/include/soc/iomap.h | 4 ++++ 2 files changed, 5 insertions(+) diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index df14a2fe91..6787642f24 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -104,6 +104,7 @@ config SOC_INTEL_PANTHERLAKE_BASE select TSC_MONOTONIC_TIMER select UDELAY_TSC select UDK_202302_BINDING + select USE_COREBOOT_FOR_BMP_RENDERING select USE_X86_64_SUPPORT select X86_INIT_NEED_1_SIPI help diff --git a/src/soc/intel/pantherlake/include/soc/iomap.h b/src/soc/intel/pantherlake/include/soc/iomap.h index 0bd56975a9..fac9c03f1c 100644 --- a/src/soc/intel/pantherlake/include/soc/iomap.h +++ b/src/soc/intel/pantherlake/include/soc/iomap.h @@ -86,6 +86,10 @@ #define IOM_BASE_SIZE 0x10000 #define IOM_BASE_ADDR_MAX 0x401080ffff /* ((IOM_BASE_ADDR + IOM_BASE_SIZE) - 1) */ +/* Temporary MMIO address for GMADR (aka LMEMBAR) with 256MB */ +#define GMADR_BASE 0xB0000000 +#define GMADR_SIZE 0x10000000 + /* I/O port address space */ #define ACPI_BASE_ADDRESS 0x1800 #define ACPI_BASE_SIZE 0x100