mb/lenovo/sklkbl: Add Lenovo Thinkpad X280 as a variant
The hardware of this machine is mostly identical to the already
supported Thinkpad Tx80 machines. Minor differences are the absence of
SODIMM slots (i.e. all RAM is soldered on), two fewer eDP lane pairs,
and different PCIe lane assignment.
All the hardware configuration settings (VBT, GPIO register dumps,
hda verbs, and so on) have been obtained running the latest BIOS/EC
firmware (1.59/N20ET74W, 1.15/N20HT28W). PCIe port assignments as well
as USB, RAM SPD and GPIO assignments have been cross-checked against
publicly available schematics (Finn-1).
Basic functionality has been validated on a Thinkpad X280 part number
20KF-002QUS with 16GB onboard RAM, i7-8650U CPU. The laptop has been
tested with SeaBIOS 1.17 as a payload booting either debian 13 or
Windows 10. A cursory check of the hardware (video, wifi, audio, wired
ethernet, reboot, sleep) shows no issues. This patch also includes a
fix for the headphone jack detection that's been already validated
on the Thinkpad T480 with commit e5d10e5d23 ("mb/lenovo/t480: Fix
headphone jack").
Change-Id: Ia8e6c40b200dee240d08d79253fbbe0842882a80
Signed-off-by: Johann C. Rode <jcrode@gmx.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/90254
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Johann C. Rode
Matt DeVillier
parent
9a3818f9b6
commit
0b4d41004d
14 changed files with 593 additions and 8 deletions
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@ -20,33 +20,41 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
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select MAINBOARD_USES_IFD_GBE_REGION
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select MEMORY_MAPPED_TPM
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select SOC_INTEL_COMMON_BLOCK_HDA_VERB
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select SOC_INTEL_KABYLAKE if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_T580
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select SOC_INTEL_SKYLAKE if BOARD_LENOVO_T470S
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select SPD_READ_BY_WORD
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select SYSTEM_TYPE_LAPTOP
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config BOARD_LENOVO_T470S
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bool
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select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
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select SOC_INTEL_SKYLAKE
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select HAVE_SPD_IN_CBFS
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config BOARD_LENOVO_T480
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bool
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select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
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select SOC_INTEL_KABYLAKE
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select MEC1653_HAS_DEBUG_UNLOCK
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select VARIANT_HAS_DGPU
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config BOARD_LENOVO_T480S
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bool
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select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
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select SOC_INTEL_KABYLAKE
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select VARIANT_HAS_DGPU
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config BOARD_LENOVO_T580
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bool
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select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
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select SOC_INTEL_KABYLAKE
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select MEC1653_HAS_DEBUG_UNLOCK
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select VARIANT_HAS_DGPU
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config BOARD_LENOVO_X280
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bool
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select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
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select SOC_INTEL_KABYLAKE
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select HAVE_SPD_IN_CBFS
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if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON
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config MAINBOARD_DIR
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@ -57,6 +65,7 @@ config VARIANT_DIR
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default "t480" if BOARD_LENOVO_T480
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default "t480s" if BOARD_LENOVO_T480S
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default "t580" if BOARD_LENOVO_T580
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default "x280" if BOARD_LENOVO_X280
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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@ -66,6 +75,7 @@ config MAINBOARD_PART_NUMBER
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default "T480" if BOARD_LENOVO_T480
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default "T480s" if BOARD_LENOVO_T480S
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default "T580" if BOARD_LENOVO_T580
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default "X280" if BOARD_LENOVO_X280
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config CBFS_SIZE
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default 0x900000
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@ -11,3 +11,6 @@ config BOARD_LENOVO_T480S
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config BOARD_LENOVO_T580
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bool "ThinkPad T580"
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config BOARD_LENOVO_X280
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bool "ThinkPad X280"
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@ -18,6 +18,11 @@ subdirs-y += variants/$(VARIANT_DIR)/memory
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subdirs-y += spd
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endif
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ifeq ($(CONFIG_BOARD_LENOVO_X280),y)
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subdirs-y += variants/$(VARIANT_DIR)/memory
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subdirs-y += spd
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endif
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ifeq ($(CONFIG_VARIANT_HAS_DGPU),y)
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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endif
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BIN
src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/data.vbt
Normal file
BIN
src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/data.vbt
Normal file
Binary file not shown.
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@ -0,0 +1,19 @@
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-- SPDX-License-Identifier: GPL-2.0-or-later
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with HW.GFX.GMA;
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with HW.GFX.GMA.Display_Probing;
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use HW.GFX.GMA;
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use HW.GFX.GMA.Display_Probing;
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private package GMA.Mainboard is
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ports : constant Port_List :=
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(eDP,
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DP1,
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DP2,
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HDMI1,
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HDMI2,
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others => Disabled);
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end GMA.Mainboard;
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200
src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gpio.c
Normal file
200
src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gpio.c
Normal file
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@ -0,0 +1,200 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <soc/gpio.h>
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#include "../../variant.h"
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Community 0 ------- */
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/* ------- GPIO Group GPP_A ------- */
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PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */
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PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */
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PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */
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PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */
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PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */
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PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */
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PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */
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PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */
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PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */
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PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */
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PAD_NC(GPP_A11, NONE),
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PAD_NC(GPP_A12, NONE),
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PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */
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PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */
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PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSACK*/
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PAD_NC(GPP_A16, NONE),
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PAD_NC(GPP_A17, NONE),
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PAD_NC(GPP_A18, NONE),
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PAD_NC(GPP_A19, NONE),
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PAD_NC(GPP_A20, NONE),
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PAD_NC(GPP_A21, NONE),
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PAD_NC(GPP_A22, NONE),
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PAD_NC(GPP_A23, NONE),
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/* ------- GPIO Group GPP_B ------- */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */
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PAD_NC(GPP_B2, NONE),
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PAD_NC(GPP_B3, NONE),
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PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (TB) */
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE1 (WLAN) */
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE2 (GBE) */
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (NVMe) */
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PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WWAN) */
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PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* -EXT_PWR_GATE */
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */
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PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */
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PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */
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PAD_NC(GPP_B16, NONE),
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PAD_NC(GPP_B17, NONE),
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PAD_NC(GPP_B18, NONE),
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PAD_NC(GPP_B19, NONE),
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PAD_NC(GPP_B20, NONE),
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PAD_NC(GPP_B21, NONE),
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PAD_NC(GPP_B22, NONE),
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PAD_NC(GPP_B23, NONE),
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/* ------- GPIO Community 1 ------- */
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/* ------- GPIO Group GPP_C ------- */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */
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PAD_NC(GPP_C2, NONE), /* -SMBALERT */
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */
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PAD_NC(GPP_C5, NONE),
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PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */
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PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */
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PAD_NC(GPP_C8, NONE),
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PAD_NC(GPP_C9, NONE),
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PAD_NC(GPP_C10, NONE),
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PAD_NC(GPP_C11, NONE),
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PAD_NC(GPP_C12, NONE),
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PAD_NC(GPP_C13, NONE),
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PAD_NC(GPP_C14, NONE),
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PAD_NC(GPP_C15, NONE),
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */
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PAD_NC(GPP_C18, NONE),
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PAD_NC(GPP_C19, NONE),
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PAD_NC(GPP_C20, NONE),
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PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */
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PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */
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PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */
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/* ------- GPIO Group GPP_D ------- */
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PAD_NC(GPP_D0, NONE),
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PAD_NC(GPP_D1, NONE),
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PAD_NC(GPP_D2, NONE),
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PAD_NC(GPP_D3, NONE),
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PAD_NC(GPP_D4, NONE),
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PAD_NC(GPP_D5, NONE),
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PAD_NC(GPP_D6, NONE),
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PAD_NC(GPP_D7, NONE),
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PAD_NC(GPP_D8, NONE),
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PAD_NC(GPP_D9, UP_20K),
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PAD_NC(GPP_D10, NONE),
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PAD_NC(GPP_D11, UP_20K),
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PAD_NC(GPP_D12, UP_20K),
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PAD_NC(GPP_D13, NONE),
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PAD_NC(GPP_D14, NONE),
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PAD_NC(GPP_D15, NONE),
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PAD_NC(GPP_D16, NONE),
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PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */
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PAD_NC(GPP_D18, NONE),
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PAD_NC(GPP_D19, NONE),
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PAD_NC(GPP_D20, NONE),
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PAD_NC(GPP_D21, NONE),
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PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */
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PAD_NC(GPP_D23, NONE),
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/* ------- GPIO Group GPP_E ------- */
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PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */
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PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -SATA1_DTCT */
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PAD_NC(GPP_E2, NONE),
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PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */
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PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */
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PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1), /* SATA1_DEVSLP */
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PAD_NC(GPP_E6, NONE),
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PAD_CFG_GPO(GPP_E7, 1, DEEP), /* -WWAN_DISABLE */
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PAD_NC(GPP_E8, NONE),
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PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */
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PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */
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PAD_NC(GPP_E11, NONE),
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PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */
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PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */
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PAD_NC(GPP_E15, NONE),
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PAD_NC(GPP_E16, NONE),
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PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */
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PAD_NC(GPP_E18, NONE),
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PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
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PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */
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PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */
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PAD_NC(GPP_E22, NONE),
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PAD_NC(GPP_E23, NONE),
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/* ------- GPIO Community 2 ------- */
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/* -------- GPIO Group GPD -------- */
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PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */
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PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */
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PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */
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PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */
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PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */
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PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */
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PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */
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PAD_NC(GPD7, NONE),
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PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */
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PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */
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PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */
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PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */
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/* ------- GPIO Community 3 ------- */
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/* ------- GPIO Group GPP_F ------- */
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PAD_NC(GPP_F0, NONE), /* NFC_ACTIVE */
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PAD_NC(GPP_F1, NONE),
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PAD_NC(GPP_F2, NONE),
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PAD_NC(GPP_F3, NONE),
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PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */
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PAD_NC(GPP_F5, UP_20K),
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PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, RSMRST, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */
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PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, RSMRST, OFF, ACPI), /* -INT_MIC_DTCT */
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PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG0 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG1 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG2 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG3 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, RSMRST, OFF, ACPI), /* PLANARID0 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, RSMRST, OFF, ACPI), /* PLANARID1 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, RSMRST, OFF, ACPI), /* PLANARID2 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, RSMRST, OFF, ACPI), /* PLANARID3 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID0 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID1 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID2 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID3 */
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PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID4 */
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PAD_NC(GPP_F21, UP_20K),
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PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, RSMRST, OFF, ACPI), /* -TAMPER_SW_DTCT */
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PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, RSMRST, OFF, ACPI), /* -SC_DTCT */
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/* ------- GPIO Group GPP_G ------- */
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PAD_NC(GPP_G0, NONE),
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PAD_NC(GPP_G1, NONE),
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PAD_NC(GPP_G2, NONE),
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PAD_NC(GPP_G3, NONE),
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PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */
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PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */
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PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */
|
||||
PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */
|
||||
|
||||
};
|
||||
|
||||
void variant_config_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
124
src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/hda_verb.c
Normal file
124
src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/hda_verb.c
Normal file
|
|
@ -0,0 +1,124 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
0x10ec0257, // Vendor/Device ID: Realtek ALC257
|
||||
0x17aa2256, // Subsystem ID
|
||||
18,
|
||||
AZALIA_SUBVENDOR(0, 0x17aa2256),
|
||||
|
||||
AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC(
|
||||
AZALIA_INTEGRATED,
|
||||
AZALIA_INTERNAL,
|
||||
AZALIA_MIC_IN,
|
||||
AZALIA_OTHER_DIGITAL,
|
||||
AZALIA_COLOR_UNKNOWN,
|
||||
AZALIA_NO_JACK_PRESENCE_DETECT,
|
||||
2, 0
|
||||
)),
|
||||
AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device
|
||||
AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC(
|
||||
AZALIA_INTEGRATED,
|
||||
AZALIA_INTERNAL,
|
||||
AZALIA_SPEAKER,
|
||||
AZALIA_OTHER_ANALOG,
|
||||
AZALIA_COLOR_UNKNOWN,
|
||||
AZALIA_NO_JACK_PRESENCE_DETECT,
|
||||
1, 0
|
||||
)),
|
||||
AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC(
|
||||
AZALIA_JACK,
|
||||
AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
|
||||
AZALIA_MIC_IN,
|
||||
AZALIA_STEREO_MONO_1_8,
|
||||
AZALIA_BLACK,
|
||||
AZALIA_JACK_PRESENCE_DETECT,
|
||||
3, 0
|
||||
)),
|
||||
AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device
|
||||
AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)),
|
||||
AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC(
|
||||
AZALIA_JACK,
|
||||
AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT,
|
||||
AZALIA_HP_OUT,
|
||||
AZALIA_STEREO_MONO_1_8,
|
||||
AZALIA_BLACK,
|
||||
AZALIA_JACK_PRESENCE_DETECT,
|
||||
1, 15
|
||||
)),
|
||||
|
||||
//==========Widget node 0x20 - 0 :Hidden register SW reset
|
||||
0x0205001A,
|
||||
0x0204C003,
|
||||
0x0205001A,
|
||||
0x0204C003,
|
||||
0x05850000,
|
||||
0x0584F880,
|
||||
0x05850000,
|
||||
0x0584F880,
|
||||
//==========Widget node 0x20 - 1 : ClassD 2W
|
||||
0x02050038,
|
||||
0x02048981,
|
||||
0x0205001B,
|
||||
0x02040A4B,
|
||||
//==========Widget node 0x20 - 2
|
||||
0x0205003C,
|
||||
0x02043154,
|
||||
0x0205003C,
|
||||
0x02043114,
|
||||
//==========Widget node 0x20 - 3 :
|
||||
0x02050046,
|
||||
0x02040004,
|
||||
0x05750003,
|
||||
0x057409A3,
|
||||
//==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD
|
||||
0x02050009,
|
||||
0x02046003,
|
||||
0x0205000A,
|
||||
0x02047770,
|
||||
//==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB)
|
||||
0x02050037,
|
||||
0x0204FE15,
|
||||
0x02050030,
|
||||
0x02049004,
|
||||
|
||||
0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI
|
||||
0x80860101, // Subsystem ID
|
||||
4,
|
||||
AZALIA_SUBVENDOR(2, 0x80860101),
|
||||
|
||||
AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC(
|
||||
AZALIA_JACK,
|
||||
AZALIA_DIGITAL_DISPLAY,
|
||||
AZALIA_DIGITAL_OTHER_OUT,
|
||||
AZALIA_OTHER_DIGITAL,
|
||||
AZALIA_COLOR_UNKNOWN,
|
||||
AZALIA_JACK_PRESENCE_DETECT,
|
||||
1, 0
|
||||
)),
|
||||
AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC(
|
||||
AZALIA_JACK,
|
||||
AZALIA_DIGITAL_DISPLAY,
|
||||
AZALIA_DIGITAL_OTHER_OUT,
|
||||
AZALIA_OTHER_DIGITAL,
|
||||
AZALIA_COLOR_UNKNOWN,
|
||||
AZALIA_JACK_PRESENCE_DETECT,
|
||||
1, 0
|
||||
)),
|
||||
AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC(
|
||||
AZALIA_JACK,
|
||||
AZALIA_DIGITAL_DISPLAY,
|
||||
AZALIA_DIGITAL_OTHER_OUT,
|
||||
AZALIA_OTHER_DIGITAL,
|
||||
AZALIA_COLOR_UNKNOWN,
|
||||
AZALIA_JACK_PRESENCE_DETECT,
|
||||
1, 0
|
||||
)),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
AZALIA_ARRAY_SIZES;
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# util/spd_tools/bin/part_id_gen TGL ddr4 src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/mem_parts_used.txt
|
||||
|
||||
SPD_SOURCES =
|
||||
SPD_SOURCES += spd/ddr4/set-0/spd-15.hex # ID = 0(0b0000) Parts = MT40A256M16GE-083E:B
|
||||
SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 1(0b0001) Parts = MT40A512M16JY-083E:B
|
||||
SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 2(0b0010) Parts = MT40A512M16JY-083E:B
|
||||
SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 3(0b0011) Parts = MT40A512M16LY-075:H
|
||||
SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 4(0b0100) Parts = MT40A512M16LY-075:H
|
||||
SPD_SOURCES += spd/ddr4/set-0/spd-13.hex # ID = 5(0b0101) Parts = MT40A1G16WBU-083E:B
|
||||
SPD_SOURCES += spd/ddr4/set-0/spd-16.hex # ID = 6(0b0110) Parts = K4A4G165WE-BCRC
|
||||
SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 7(0b0111) Parts = K4A8G165WC-BCRC
|
||||
SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 8(0b1000) Parts = K4A8G165WC-BCRC
|
||||
SPD_SOURCES += spd/ddr4/set-0/spd-14.hex # ID = 9(0b1001) Parts = K4AAG165WB-MCRC
|
||||
SPD_SOURCES += spd/ddr4/set-0/spd-16.hex # ID = 10(0b1010) Parts = H5AN4G6NAFR-UHC
|
||||
SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 11(0b1011) Parts = H5AN8G6NAFR-UHC
|
||||
SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 12(0b1100) Parts = H5AN8G6NAFR-UHC
|
||||
SPD_SOURCES += spd/ddr4/set-0/spd-17.hex # ID = 13(0b1101) Parts = H5ANAG6NAMR-UHC
|
||||
SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 14(0b1110) Parts = MT40A512M16LY-075:E
|
||||
SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 15(0b1111) Parts = MT40A512M16LY-075:E
|
||||
|
|
@ -0,0 +1,22 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-or-later
|
||||
# This is an auto-generated file. Do not edit!!
|
||||
# Generated by:
|
||||
# util/spd_tools/bin/part_id_gen TGL ddr4 src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/mem_parts_used.txt
|
||||
|
||||
DRAM Part Name ID to assign
|
||||
MT40A256M16GE-083E:B 0 (0000)
|
||||
MT40A512M16JY-083E:B 1 (0001)
|
||||
MT40A512M16JY-083E:B 2 (0010)
|
||||
MT40A512M16LY-075:H 3 (0011)
|
||||
MT40A512M16LY-075:H 4 (0100)
|
||||
MT40A1G16WBU-083E:B 5 (0101)
|
||||
K4A4G165WE-BCRC 6 (0110)
|
||||
K4A8G165WC-BCRC 7 (0111)
|
||||
K4A8G165WC-BCRC 8 (1000)
|
||||
K4AAG165WB-MCRC 9 (1001)
|
||||
H5AN4G6NAFR-UHC 10 (1010)
|
||||
H5AN8G6NAFR-UHC 11 (1011)
|
||||
H5AN8G6NAFR-UHC 12 (1100)
|
||||
H5ANAG6NAMR-UHC 13 (1101)
|
||||
MT40A512M16LY-075:E 14 (1110)
|
||||
MT40A512M16LY-075:E 15 (1111)
|
||||
|
|
@ -0,0 +1,16 @@
|
|||
MT40A256M16GE-083E:B,0
|
||||
MT40A512M16JY-083E:B,1
|
||||
MT40A512M16JY-083E:B,2
|
||||
MT40A512M16LY-075:H,3
|
||||
MT40A512M16LY-075:H,4
|
||||
MT40A1G16WBU-083E:B,5
|
||||
K4A4G165WE-BCRC,6
|
||||
K4A8G165WC-BCRC,7
|
||||
K4A8G165WC-BCRC,8
|
||||
K4AAG165WB-MCRC,9
|
||||
H5AN4G6NAFR-UHC,10
|
||||
H5AN8G6NAFR-UHC,11
|
||||
H5AN8G6NAFR-UHC,12
|
||||
H5ANAG6NAMR-UHC,13
|
||||
MT40A512M16LY-075:E,14
|
||||
MT40A512M16LY-075:E,15
|
||||
|
|
@ -0,0 +1,57 @@
|
|||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <cbfs.h>
|
||||
#include <gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <spd_bin.h>
|
||||
#include <stdio.h>
|
||||
#include "../../spd/spd.h"
|
||||
#include "../../variant.h"
|
||||
|
||||
static const struct pad_config memory_id_gpio_table[] = {
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */
|
||||
PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */
|
||||
};
|
||||
|
||||
uint8_t variant_memory_sku(void)
|
||||
{
|
||||
gpio_t spd_gpios[] = {
|
||||
GPP_F16,
|
||||
GPP_F17,
|
||||
GPP_F18,
|
||||
GPP_F19,
|
||||
GPP_F20,
|
||||
};
|
||||
|
||||
return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
|
||||
}
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
uint8_t spd_idx;
|
||||
|
||||
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
|
||||
mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */
|
||||
mem_cfg->DqPinsInterleaved = false; /* DDR_DQ in non-interleave mode */
|
||||
mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE;
|
||||
|
||||
/* Get SPD for soldered RAM SPD (CH 1 and 2) */
|
||||
gpio_configure_pads(memory_id_gpio_table, ARRAY_SIZE(memory_id_gpio_table));
|
||||
|
||||
spd_idx = variant_memory_sku();
|
||||
printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx);
|
||||
mem_cfg->MemorySpdPtr00 = (uintptr_t)mainboard_find_spd_data(spd_idx);
|
||||
switch (spd_idx) {
|
||||
case 1: case 3: case 7: case 11: case 14:
|
||||
printk(BIOS_DEBUG, "Detected single channel\n");
|
||||
break;
|
||||
default:
|
||||
printk(BIOS_DEBUG, "Detected dual channel\n");
|
||||
mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00;
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -0,0 +1,85 @@
|
|||
# SPDX-License-Identifier: GPL-2.0-only
|
||||
|
||||
chip soc/intel/skylake
|
||||
device domain 0 on
|
||||
device ref south_xhci on
|
||||
register "usb2_ports" = "{
|
||||
[0] = USB2_PORT_MID(OC0), // JUSB1 (USB-A always on)
|
||||
[1] = USB2_PORT_MID(OC1), // JUSB2 (USB-A)
|
||||
[2] = USB2_PORT_MID(OC_SKIP), // JFPR (smartcard slot)
|
||||
[3] = USB2_PORT_MID(OC_SKIP), // JUSBC (USB docking station)
|
||||
[4] = USB2_PORT_MID(OC_SKIP), // JIRCAM (IR camera)
|
||||
[5] = USB2_PORT_MID(OC_SKIP), // JWWAN (M.2 WWAN USB)
|
||||
[6] = USB2_PORT_MID(OC_SKIP), // JWLAN (M.2 WLAN USB)
|
||||
[7] = USB2_PORT_MID(OC_SKIP), // JCAM (webcam)
|
||||
[8] = USB2_PORT_MID(OC_SKIP), // JFPR (fingerprint reader)
|
||||
[9] = USB2_PORT_MID(OC_SKIP), // JLCD (touch panel)
|
||||
}"
|
||||
register "usb3_ports" = "{
|
||||
[0] = USB3_PORT_DEFAULT(OC0), // JUSB1 (USB-A always on)
|
||||
[1] = USB3_PORT_DEFAULT(OC1), // JUSB2 (USB-A)
|
||||
[2] = USB3_PORT_DEFAULT(OC_SKIP), // JSD (SD card reader)
|
||||
[3] = USB3_PORT_DEFAULT(OC_SKIP), // JUSB3 (USB docking station)
|
||||
}"
|
||||
end
|
||||
|
||||
# PCIe
|
||||
# PCIe Controller 1 - 1x2 + 2x1
|
||||
# PCIE 1-2 - RP1 - TB - CLKOUT0 - CLKREQ0
|
||||
# PCIE 3 - RP3 - WLAN - CLKOUT1 - CLKREQ1
|
||||
# PCIE 4 - GbE - GbE - CLKOUT2 - CLKREQ2
|
||||
# PCIe Controller 2 - 1x4
|
||||
# PCIE 5-8 - RP5 - NVMe - CLKOUT3 - CLKREQ3
|
||||
# PCIe Controller 3 - 4x1
|
||||
# PCIE 12 - RP9 - WWAN - CLKOUT5 - CLKREQ5
|
||||
|
||||
# TB - x2
|
||||
device ref pcie_rp1 on
|
||||
register "PcieRpClkReqSupport[0]" = "true"
|
||||
register "PcieRpClkReqNumber[0]" = "0"
|
||||
register "PcieRpClkSrcNumber[0]" = "0"
|
||||
register "PcieRpAdvancedErrorReporting[0]" = "true"
|
||||
register "PcieRpHotPlug[0]" = "true"
|
||||
end
|
||||
|
||||
# M.2 WLAN x1
|
||||
device ref pcie_rp3 on
|
||||
register "PcieRpClkReqSupport[2]" = "true"
|
||||
register "PcieRpClkReqNumber[2]" = "1"
|
||||
register "PcieRpClkSrcNumber[2]" = "1"
|
||||
register "PcieRpAdvancedErrorReporting[2]" = "true"
|
||||
register "PcieRpLtrEnable[2]" = "true"
|
||||
smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
|
||||
end
|
||||
|
||||
# Ethernet (clobbers RP4)
|
||||
device ref gbe on
|
||||
register "LanClkReqSupported" = "true"
|
||||
register "LanClkReqNumber" = "2"
|
||||
register "PcieRpClkReqNumber[3]" = "2"
|
||||
register "PcieRpClkSrcNumber[3]" = "2"
|
||||
register "EnableLanLtr" = "true"
|
||||
register "EnableLanK1Off" = "true"
|
||||
end
|
||||
|
||||
# M.2 2280 SSD - x4 (RP9)
|
||||
device ref pcie_rp5 on
|
||||
register "PcieRpClkReqSupport[4]" = "true"
|
||||
register "PcieRpClkReqNumber[4]" = "3"
|
||||
register "PcieRpClkSrcNumber[4]" = "3"
|
||||
register "PcieRpAdvancedErrorReporting[4]" = "true"
|
||||
register "PcieRpLtrEnable[4]" = "true"
|
||||
smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X"
|
||||
end
|
||||
|
||||
# M.2 WLAN x1
|
||||
device ref pcie_rp9 on
|
||||
register "PcieRpClkReqSupport[8]" = "true"
|
||||
register "PcieRpClkReqNumber[8]" = "5"
|
||||
register "PcieRpClkSrcNumber[8]" = "5"
|
||||
register "PcieRpAdvancedErrorReporting[8]" = "true"
|
||||
register "PcieRpLtrEnable[8]" = "true"
|
||||
smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X"
|
||||
end
|
||||
end
|
||||
end
|
||||
Loading…
Add table
Add a link
Reference in a new issue