diff --git a/Documentation/mainboard/index.md b/Documentation/mainboard/index.md index 1b2697c9c0..bbfe831fc9 100644 --- a/Documentation/mainboard/index.md +++ b/Documentation/mainboard/index.md @@ -248,7 +248,7 @@ T440p ```{toctree} :maxdepth: 1 -T470s/T480/T480s/T580 +T470s/T480/T480s/T580/X280 ``` ## Libretrend diff --git a/Documentation/mainboard/lenovo/skylake.md b/Documentation/mainboard/lenovo/skylake.md index 18e741daa0..64e075e2cd 100644 --- a/Documentation/mainboard/lenovo/skylake.md +++ b/Documentation/mainboard/lenovo/skylake.md @@ -1,7 +1,7 @@ -# Lenovo ThinkPad T470s/T480/T480s/T580 +# Lenovo ThinkPad T470s/T480/T480s/T580/X280 This page describes how to run coreboot on the Lenovo [Thinkpad T470s], [ThinkPad T480], -[Thinkpad T480s], and [Thinkpad T580]. +[Thinkpad T480s], [Thinkpad T580], and [Thinkpad X280]. ## Important Notes @@ -105,10 +105,12 @@ firmware image from the updater: python Dell_PFS_Extract.py Inspiron_5468_1.3.0.exe -The resulting binary should be renamed `me_donor.bin` and moved to the `binaries` folder with -the IFD and GBE binaries. +The resulting binary should be renamed `me_donor.bin` (file size 0x1f0000 bytes, sha256 +`912271bb3ff2cf0e2e27ccfb94337baaca027e6c90b4245f9807a592c8a652e1`) and moved to the `binaries` +folder with the IFD and GBE binaries. -Then, generate the deguarded ME firmware image adjusting the `--delta` argument accordingly: +Then, generate the deguarded ME firmware image adjusting the `--delta` argument according to +your laptop's model: ./finalimage.py --delta data/delta/thinkpad_t480 --version 11.6.0.1126 --pch LP --sku 2M --fake-fpfs data/fpfs/zero --input ../coreboot/binaries/me_donor.bin --output ../coreboot/binaries/me_deguarded.bin @@ -131,6 +133,25 @@ HAP bit in the IFD using `ifdtool`: The modified IFD will be saved as `ifd.bin.new`. Rename the original file to `ifd.bin.orig` and the HAP-enabled one to `ifd.bin` +If you want to allocate the space that has become available from truncating the ME firmware to +corebios, you can modify the IFD layout. First, save the layout below into a text file +`layout.txt`: + + 00000000:00000fff fd + 001f4000:00ffffff bios + 00003000:001f3fff me + 00001000:00002fff gbe + +Then run ifdtool again: + + util/ifdtool/ifdtool -p sklkbl -n layout.txt binaries/ifd.bin + +Once again, the modified IFD will be saved as `ifd.bin.new`. Rename `ifd.bin.new` to `ifd.bin`. + +The layout above allows you to maximize the CBFS size in your coreboot `.config`: + + CONFIG_CBFS_SIZE=0xE0C000 + ## Building coreboot You can use `make menuconfig` or `make nconfig` to select the mainboard matching your machine, @@ -204,6 +225,7 @@ binaries if only flashing the `bios` region. [ThinkPad T480]: https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480-type-20l5-20l6/ [ThinkPad T480s]: https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480s-type-20l7-20l8/ [Thinkpad T580]: https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t580-type-20l9-20la/ +[Thinkpad X280]: https://pcsupport.lenovo.com/us/en/products/laptops-and-netbooks/thinkpad-x-series-laptops/thinkpad-x280-type-20kf-20ke/ [on Lenovo's site]: https://support.lenovo.com/us/en/downloads/ds502355-bios-update-utility-bootable-cd-for-windows-10-64-bit-linux-thinkpad-t480 [from Lenovo's site]: https://pcsupport.lenovo.com/gb/en/products/laptops-and-netbooks/thinkpad-t-series-laptops/thinkpad-t480s-type-20l7-20l8/solutions/ht508988-critical-intel-thunderbolt-software-and-firmware-updates-thinkpad [how to externally flash the TB3 firmware]: https://libreboot.org/docs/install/t480.html#thunderbolt-issue-read-this-before-flashing diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig index 8db4676391..d69d94f638 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig +++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig @@ -20,33 +20,41 @@ config BOARD_LENOVO_SKLKBL_THINKPAD_COMMON select MAINBOARD_USES_IFD_GBE_REGION select MEMORY_MAPPED_TPM select SOC_INTEL_COMMON_BLOCK_HDA_VERB - select SOC_INTEL_KABYLAKE if BOARD_LENOVO_T480 || BOARD_LENOVO_T480S || BOARD_LENOVO_T580 - select SOC_INTEL_SKYLAKE if BOARD_LENOVO_T470S select SPD_READ_BY_WORD select SYSTEM_TYPE_LAPTOP config BOARD_LENOVO_T470S bool select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON + select SOC_INTEL_SKYLAKE select HAVE_SPD_IN_CBFS config BOARD_LENOVO_T480 bool select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON + select SOC_INTEL_KABYLAKE select MEC1653_HAS_DEBUG_UNLOCK select VARIANT_HAS_DGPU config BOARD_LENOVO_T480S bool select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON + select SOC_INTEL_KABYLAKE select VARIANT_HAS_DGPU config BOARD_LENOVO_T580 bool select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON + select SOC_INTEL_KABYLAKE select MEC1653_HAS_DEBUG_UNLOCK select VARIANT_HAS_DGPU +config BOARD_LENOVO_X280 + bool + select BOARD_LENOVO_SKLKBL_THINKPAD_COMMON + select SOC_INTEL_KABYLAKE + select HAVE_SPD_IN_CBFS + if BOARD_LENOVO_SKLKBL_THINKPAD_COMMON config MAINBOARD_DIR @@ -57,6 +65,7 @@ config VARIANT_DIR default "t480" if BOARD_LENOVO_T480 default "t480s" if BOARD_LENOVO_T480S default "t580" if BOARD_LENOVO_T580 + default "x280" if BOARD_LENOVO_X280 config OVERRIDE_DEVICETREE default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb" @@ -66,6 +75,7 @@ config MAINBOARD_PART_NUMBER default "T480" if BOARD_LENOVO_T480 default "T480s" if BOARD_LENOVO_T480S default "T580" if BOARD_LENOVO_T580 + default "X280" if BOARD_LENOVO_X280 config CBFS_SIZE default 0x900000 diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name index 26c4a3c65b..1d2888840f 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name +++ b/src/mainboard/lenovo/sklkbl_thinkpad/Kconfig.name @@ -11,3 +11,6 @@ config BOARD_LENOVO_T480S config BOARD_LENOVO_T580 bool "ThinkPad T580" + +config BOARD_LENOVO_X280 + bool "ThinkPad X280" diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk index 8d530b7416..eebe6f457d 100644 --- a/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk +++ b/src/mainboard/lenovo/sklkbl_thinkpad/Makefile.mk @@ -18,6 +18,11 @@ subdirs-y += variants/$(VARIANT_DIR)/memory subdirs-y += spd endif +ifeq ($(CONFIG_BOARD_LENOVO_X280),y) +subdirs-y += variants/$(VARIANT_DIR)/memory +subdirs-y += spd +endif + ifeq ($(CONFIG_VARIANT_HAS_DGPU),y) CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include endif diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/data.vbt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/data.vbt new file mode 100644 index 0000000000..bfb312850e Binary files /dev/null and b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/data.vbt differ diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gma-mainboard.ads b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gma-mainboard.ads new file mode 100644 index 0000000000..fcfbd75a92 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (eDP, + DP1, + DP2, + HDMI1, + HDMI2, + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gpio.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gpio.c new file mode 100644 index 0000000000..f38734be85 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/gpio.c @@ -0,0 +1,200 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include "../../variant.h" + +static const struct pad_config gpio_table[] = { + /* ------- GPIO Community 0 ------- */ + + /* ------- GPIO Group GPP_A ------- */ + PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1), /* -KBRC */ + PAD_CFG_NF(GPP_A1, NATIVE, DEEP, NF1), /* LPC_AD0 */ + PAD_CFG_NF(GPP_A2, NATIVE, DEEP, NF1), /* LPC_AD1 */ + PAD_CFG_NF(GPP_A3, NATIVE, DEEP, NF1), /* LPC_AD2 */ + PAD_CFG_NF(GPP_A4, NATIVE, DEEP, NF1), /* LPC_AD3 */ + PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1), /* -LPC_FRAME */ + PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), /* IRQSER */ + PAD_CFG_NF(GPP_A7, NONE, DEEP, NF1), /* -TPM_IRQ */ + PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1), /* -CLKRUN */ + PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), /* LPCCLK_EC_24M */ + PAD_CFG_NF(GPP_A10, DN_20K, DEEP, NF1), /* LPCCLK_DEBUG_24M */ + PAD_NC(GPP_A11, NONE), + PAD_NC(GPP_A12, NONE), + PAD_CFG_NF(GPP_A13, NATIVE, DEEP, NF1), /* -SUSWARN */ + PAD_CFG_NF(GPP_A14, NATIVE, DEEP, NF1), /* -SUS_STAT */ + PAD_CFG_NF(GPP_A15, NATIVE, DEEP, NF1), /* -SUSACK*/ + PAD_NC(GPP_A16, NONE), + PAD_NC(GPP_A17, NONE), + PAD_NC(GPP_A18, NONE), + PAD_NC(GPP_A19, NONE), + PAD_NC(GPP_A20, NONE), + PAD_NC(GPP_A21, NONE), + PAD_NC(GPP_A22, NONE), + PAD_NC(GPP_A23, NONE), + + /* ------- GPIO Group GPP_B ------- */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), /* CORE_VID0 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), /* CORE_VID1 */ + PAD_NC(GPP_B2, NONE), + PAD_NC(GPP_B3, NONE), + PAD_CFG_GPI_SCI(GPP_B4, NONE, DEEP, EDGE_SINGLE, INVERT), /* -TBT_PLUG_EVENT */ + PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), /* -CLKREQ_PCIE0 (TB) */ + PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* -CLKREQ_PCIE1 (WLAN) */ + PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* -CLKREQ_PCIE2 (GBE) */ + PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), /* -CLKREQ_PCIE3 (NVMe) */ + PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_B10, NONE, DEEP, NF1), /* -CLKREQ_PCIE5 (WWAN) */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), /* -EXT_PWR_GATE */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), /* -PCH_SLP_S0 */ + PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), /* -PLTRST */ + PAD_CFG_NF(GPP_B14, NATIVE, DEEP, NF1), /* PCH_SPKR */ + PAD_CFG_GPO(GPP_B15, 0, DEEP), /* NFC_DLREQ */ + PAD_NC(GPP_B16, NONE), + PAD_NC(GPP_B17, NONE), + PAD_NC(GPP_B18, NONE), + PAD_NC(GPP_B19, NONE), + PAD_NC(GPP_B20, NONE), + PAD_NC(GPP_B21, NONE), + PAD_NC(GPP_B22, NONE), + PAD_NC(GPP_B23, NONE), + + /* ------- GPIO Community 1 ------- */ + + /* ------- GPIO Group GPP_C ------- */ + PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* SMB_CLK */ + PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* SMB_DATA */ + PAD_NC(GPP_C2, NONE), /* -SMBALERT */ + PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), /* SML0_CLK */ + PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), /* SML0_DATA */ + PAD_NC(GPP_C5, NONE), + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), /* EC_SCL2 */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), /* EC_SDA2 */ + PAD_NC(GPP_C8, NONE), + PAD_NC(GPP_C9, NONE), + PAD_NC(GPP_C10, NONE), + PAD_NC(GPP_C11, NONE), + PAD_NC(GPP_C12, NONE), + PAD_NC(GPP_C13, NONE), + PAD_NC(GPP_C14, NONE), + PAD_NC(GPP_C15, NONE), + PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* I2C0_DATA */ + PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* I2C0_CLK */ + PAD_NC(GPP_C18, NONE), + PAD_NC(GPP_C19, NONE), + PAD_NC(GPP_C20, NONE), + PAD_CFG_GPO(GPP_C21, 0, DEEP), /* TBT_FORCE_PWR */ + PAD_CFG_GPI_SCI(GPP_C22, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_SCI */ + PAD_CFG_GPI_SCI(GPP_C23, NONE, DEEP, EDGE_SINGLE, INVERT), /* -EC_WAKE */ + + /* ------- GPIO Group GPP_D ------- */ + PAD_NC(GPP_D0, NONE), + PAD_NC(GPP_D1, NONE), + PAD_NC(GPP_D2, NONE), + PAD_NC(GPP_D3, NONE), + PAD_NC(GPP_D4, NONE), + PAD_NC(GPP_D5, NONE), + PAD_NC(GPP_D6, NONE), + PAD_NC(GPP_D7, NONE), + PAD_NC(GPP_D8, NONE), + PAD_NC(GPP_D9, UP_20K), + PAD_NC(GPP_D10, NONE), + PAD_NC(GPP_D11, UP_20K), + PAD_NC(GPP_D12, UP_20K), + PAD_NC(GPP_D13, NONE), + PAD_NC(GPP_D14, NONE), + PAD_NC(GPP_D15, NONE), + PAD_NC(GPP_D16, NONE), + PAD_CFG_GPO(GPP_D17, 0, DEEP), /* DDI_PRIORITY */ + PAD_NC(GPP_D18, NONE), + PAD_NC(GPP_D19, NONE), + PAD_NC(GPP_D20, NONE), + PAD_NC(GPP_D21, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_D22, UP_20K, DEEP, OFF, ACPI), /* -NFC_DTCT */ + PAD_NC(GPP_D23, NONE), + + /* ------- GPIO Group GPP_E ------- */ + PAD_CFG_GPO(GPP_E0, 1, DEEP), /* BDC_ON */ + PAD_CFG_NF(GPP_E1, NONE, DEEP, NF1), /* -SATA1_DTCT */ + PAD_NC(GPP_E2, NONE), + PAD_CFG_GPI_TRIG_OWN(GPP_E3, NONE, DEEP, EDGE_SINGLE, ACPI), /* -TBT_PLUG_EVENT */ + PAD_CFG_GPO(GPP_E4, 1, DEEP), /* NFC_ON */ + PAD_CFG_NF(GPP_E5, NONE, RSMRST, NF1), /* SATA1_DEVSLP */ + PAD_NC(GPP_E6, NONE), + PAD_CFG_GPO(GPP_E7, 1, DEEP), /* -WWAN_DISABLE */ + PAD_NC(GPP_E8, NONE), + PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* -USB_PORT0_OC0 */ + PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), /* -USB_PORT1_OC1 */ + PAD_NC(GPP_E11, NONE), + PAD_CFG_GPI_APIC_HIGH(GPP_E12, NONE, DEEP), /* NFC_INT */ + PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1), /* DDIP1_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), /* DDIP2_HPD */ + PAD_NC(GPP_E15, NONE), + PAD_NC(GPP_E16, NONE), + PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1), /* EDP_HPD */ + PAD_NC(GPP_E18, NONE), + PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1), + PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1), /* DDIP2_CTRLCLK */ + PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1), /* DDIP2_CTRLDATA */ + PAD_NC(GPP_E22, NONE), + PAD_NC(GPP_E23, NONE), + + /* ------- GPIO Community 2 ------- */ + + /* -------- GPIO Group GPD -------- */ + PAD_CFG_NF(GPD0, NONE, PWROK, NF1), /* -BATLOW */ + PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), /* AC_PRESENT */ + PAD_CFG_NF(GPD2, NATIVE, PWROK, NF1), /* -LANWAKE */ + PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), /* -PWRSW_EC */ + PAD_CFG_NF(GPD4, NONE, PWROK, NF1), /* -PCH_SLP_S3 */ + PAD_CFG_NF(GPD5, NONE, PWROK, NF1), /* -PCH_SLP_S4 */ + PAD_CFG_NF(GPD6, NONE, PWROK, NF1), /* -PCH_SLP_M */ + PAD_NC(GPD7, NONE), + PAD_CFG_NF(GPD8, NONE, PWROK, NF1), /* SUSCLK_32K */ + PAD_CFG_NF(GPD9, NONE, PWROK, NF1), /* -PCH_SLP_WLAN */ + PAD_CFG_NF(GPD10, NONE, PWROK, NF1), /* -PCH_SLP_S5 */ + PAD_CFG_NF(GPD11, NONE, PWROK, NF1), /* LANPHYPC */ + + /* ------- GPIO Community 3 ------- */ + + /* ------- GPIO Group GPP_F ------- */ + PAD_NC(GPP_F0, NONE), /* NFC_ACTIVE */ + PAD_NC(GPP_F1, NONE), + PAD_NC(GPP_F2, NONE), + PAD_NC(GPP_F3, NONE), + PAD_NC(GPP_F4, NONE), /* -WWAN_RESET */ + PAD_NC(GPP_F5, UP_20K), + PAD_CFG_GPI_TRIG_OWN(GPP_F6, UP_20K, RSMRST, OFF, ACPI), /* -MIC_HW_EN (R961 to GND) */ + PAD_CFG_GPI_TRIG_OWN(GPP_F7, UP_20K, RSMRST, OFF, ACPI), /* -INT_MIC_DTCT */ + PAD_CFG_GPI_TRIG_OWN(GPP_F8, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG0 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F9, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG1 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F10, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG2 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F11, UP_20K, RSMRST, OFF, ACPI), /* WWAN_CFG3 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F12, UP_20K, RSMRST, OFF, ACPI), /* PLANARID0 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F13, UP_20K, RSMRST, OFF, ACPI), /* PLANARID1 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F14, UP_20K, RSMRST, OFF, ACPI), /* PLANARID2 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F15, UP_20K, RSMRST, OFF, ACPI), /* PLANARID3 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID0 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID1 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID2 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID3 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, RSMRST, OFF, ACPI), /* MEMORYID4 */ + PAD_NC(GPP_F21, UP_20K), + PAD_CFG_GPI_TRIG_OWN(GPP_F22, UP_20K, RSMRST, OFF, ACPI), /* -TAMPER_SW_DTCT */ + PAD_CFG_GPI_TRIG_OWN(GPP_F23, UP_20K, RSMRST, OFF, ACPI), /* -SC_DTCT */ + + /* ------- GPIO Group GPP_G ------- */ + PAD_NC(GPP_G0, NONE), + PAD_NC(GPP_G1, NONE), + PAD_NC(GPP_G2, NONE), + PAD_NC(GPP_G3, NONE), + PAD_CFG_GPO(GPP_G4, 0, DEEP), /* TBT_RTD3_PWR_EN */ + PAD_CFG_GPO(GPP_G5, 0, DEEP), /* TBT_FORCE_USB_PWR */ + PAD_CFG_GPO(GPP_G6, 0, DEEP), /* -TBT_PERST */ + PAD_CFG_GPI_SCI(GPP_G7, NONE, DEEP, LEVEL, INVERT), /* -TBT_PCIE_WAKE */ + +}; + +void variant_config_gpios(void) +{ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); +} diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/hda_verb.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/hda_verb.c new file mode 100644 index 0000000000..089e605eaf --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/hda_verb.c @@ -0,0 +1,124 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0257, // Vendor/Device ID: Realtek ALC257 + 0x17aa2256, // Subsystem ID + 18, + AZALIA_SUBVENDOR(0, 0x17aa2256), + + AZALIA_PIN_CFG(0, 0x12, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL, + AZALIA_MIC_IN, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 2, 0 + )), + AZALIA_PIN_CFG(0, 0x13, 0x40000000), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x14, AZALIA_PIN_DESC( + AZALIA_INTEGRATED, + AZALIA_INTERNAL, + AZALIA_SPEAKER, + AZALIA_OTHER_ANALOG, + AZALIA_COLOR_UNKNOWN, + AZALIA_NO_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(0, 0x18, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x19, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_MIC_IN, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 3, 0 + )), + AZALIA_PIN_CFG(0, 0x1a, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1b, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x1d, 0x40661b45), // does not describe a jack or internal device + AZALIA_PIN_CFG(0, 0x1e, AZALIA_PIN_CFG_NC(0)), + AZALIA_PIN_CFG(0, 0x21, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_EXTERNAL_PRIMARY_CHASSIS | AZALIA_RIGHT, + AZALIA_HP_OUT, + AZALIA_STEREO_MONO_1_8, + AZALIA_BLACK, + AZALIA_JACK_PRESENCE_DETECT, + 1, 15 + )), + + //==========Widget node 0x20 - 0 :Hidden register SW reset + 0x0205001A, + 0x0204C003, + 0x0205001A, + 0x0204C003, + 0x05850000, + 0x0584F880, + 0x05850000, + 0x0584F880, + //==========Widget node 0x20 - 1 : ClassD 2W + 0x02050038, + 0x02048981, + 0x0205001B, + 0x02040A4B, + //==========Widget node 0x20 - 2 + 0x0205003C, + 0x02043154, + 0x0205003C, + 0x02043114, + //==========Widget node 0x20 - 3 : + 0x02050046, + 0x02040004, + 0x05750003, + 0x057409A3, + //==========Widget node 0x20 - 4 :JD1 enable 1JD port for HP JD + 0x02050009, + 0x02046003, + 0x0205000A, + 0x02047770, + //==========Widget node 0x20 - 5 : Silence data mode Threshold (-84dB) + 0x02050037, + 0x0204FE15, + 0x02050030, + 0x02049004, + + 0x8086280b, // Vendor/Device ID: Intel Kabylake HDMI + 0x80860101, // Subsystem ID + 4, + AZALIA_SUBVENDOR(2, 0x80860101), + + AZALIA_PIN_CFG(2, 0x05, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x06, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), + AZALIA_PIN_CFG(2, 0x07, AZALIA_PIN_DESC( + AZALIA_JACK, + AZALIA_DIGITAL_DISPLAY, + AZALIA_DIGITAL_OTHER_OUT, + AZALIA_OTHER_DIGITAL, + AZALIA_COLOR_UNKNOWN, + AZALIA_JACK_PRESENCE_DETECT, + 1, 0 + )), +}; + +const u32 pc_beep_verbs[] = {}; +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/Makefile.mk b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/Makefile.mk new file mode 100644 index 0000000000..cba70e22ac --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/Makefile.mk @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen TGL ddr4 src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/mem_parts_used.txt + +SPD_SOURCES = +SPD_SOURCES += spd/ddr4/set-0/spd-15.hex # ID = 0(0b0000) Parts = MT40A256M16GE-083E:B +SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 1(0b0001) Parts = MT40A512M16JY-083E:B +SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 2(0b0010) Parts = MT40A512M16JY-083E:B +SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 3(0b0011) Parts = MT40A512M16LY-075:H +SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 4(0b0100) Parts = MT40A512M16LY-075:H +SPD_SOURCES += spd/ddr4/set-0/spd-13.hex # ID = 5(0b0101) Parts = MT40A1G16WBU-083E:B +SPD_SOURCES += spd/ddr4/set-0/spd-16.hex # ID = 6(0b0110) Parts = K4A4G165WE-BCRC +SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 7(0b0111) Parts = K4A8G165WC-BCRC +SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 8(0b1000) Parts = K4A8G165WC-BCRC +SPD_SOURCES += spd/ddr4/set-0/spd-14.hex # ID = 9(0b1001) Parts = K4AAG165WB-MCRC +SPD_SOURCES += spd/ddr4/set-0/spd-16.hex # ID = 10(0b1010) Parts = H5AN4G6NAFR-UHC +SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 11(0b1011) Parts = H5AN8G6NAFR-UHC +SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 12(0b1100) Parts = H5AN8G6NAFR-UHC +SPD_SOURCES += spd/ddr4/set-0/spd-17.hex # ID = 13(0b1101) Parts = H5ANAG6NAMR-UHC +SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 14(0b1110) Parts = MT40A512M16LY-075:E +SPD_SOURCES += spd/ddr4/set-0/spd-12.hex # ID = 15(0b1111) Parts = MT40A512M16LY-075:E diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/dram_id.generated.txt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/dram_id.generated.txt new file mode 100644 index 0000000000..8a4e39e2c6 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/dram_id.generated.txt @@ -0,0 +1,22 @@ +# SPDX-License-Identifier: GPL-2.0-or-later +# This is an auto-generated file. Do not edit!! +# Generated by: +# util/spd_tools/bin/part_id_gen TGL ddr4 src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/mem_parts_used.txt + +DRAM Part Name ID to assign +MT40A256M16GE-083E:B 0 (0000) +MT40A512M16JY-083E:B 1 (0001) +MT40A512M16JY-083E:B 2 (0010) +MT40A512M16LY-075:H 3 (0011) +MT40A512M16LY-075:H 4 (0100) +MT40A1G16WBU-083E:B 5 (0101) +K4A4G165WE-BCRC 6 (0110) +K4A8G165WC-BCRC 7 (0111) +K4A8G165WC-BCRC 8 (1000) +K4AAG165WB-MCRC 9 (1001) +H5AN4G6NAFR-UHC 10 (1010) +H5AN8G6NAFR-UHC 11 (1011) +H5AN8G6NAFR-UHC 12 (1100) +H5ANAG6NAMR-UHC 13 (1101) +MT40A512M16LY-075:E 14 (1110) +MT40A512M16LY-075:E 15 (1111) diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/mem_parts_used.txt b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/mem_parts_used.txt new file mode 100644 index 0000000000..0f33b84f84 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory/mem_parts_used.txt @@ -0,0 +1,16 @@ +MT40A256M16GE-083E:B,0 +MT40A512M16JY-083E:B,1 +MT40A512M16JY-083E:B,2 +MT40A512M16LY-075:H,3 +MT40A512M16LY-075:H,4 +MT40A1G16WBU-083E:B,5 +K4A4G165WE-BCRC,6 +K4A8G165WC-BCRC,7 +K4A8G165WC-BCRC,8 +K4AAG165WB-MCRC,9 +H5AN4G6NAFR-UHC,10 +H5AN8G6NAFR-UHC,11 +H5AN8G6NAFR-UHC,12 +H5ANAG6NAMR-UHC,13 +MT40A512M16LY-075:E,14 +MT40A512M16LY-075:E,15 diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory_init_params.c b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory_init_params.c new file mode 100644 index 0000000000..f14d69a105 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/memory_init_params.c @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include "../../spd/spd.h" +#include "../../variant.h" + +static const struct pad_config memory_id_gpio_table[] = { + PAD_CFG_GPI_TRIG_OWN(GPP_F16, UP_20K, DEEP, OFF, ACPI), /* MEMORYID0 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F17, UP_20K, DEEP, OFF, ACPI), /* MEMORYID1 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F18, UP_20K, DEEP, OFF, ACPI), /* MEMORYID2 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F19, UP_20K, DEEP, OFF, ACPI), /* MEMORYID3 */ + PAD_CFG_GPI_TRIG_OWN(GPP_F20, UP_20K, DEEP, OFF, ACPI), /* MEMORYID4 */ +}; + +uint8_t variant_memory_sku(void) +{ + gpio_t spd_gpios[] = { + GPP_F16, + GPP_F17, + GPP_F18, + GPP_F19, + GPP_F20, + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + uint8_t spd_idx; + + FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig; + mem_cfg->CaVrefConfig = 2; /* VREF_CA to CH_A and VREF_DQ_B to CH_B */ + mem_cfg->DqPinsInterleaved = false; /* DDR_DQ in non-interleave mode */ + mem_cfg->MemorySpdDataLen = CONFIG_DIMM_SPD_SIZE; + + /* Get SPD for soldered RAM SPD (CH 1 and 2) */ + gpio_configure_pads(memory_id_gpio_table, ARRAY_SIZE(memory_id_gpio_table)); + + spd_idx = variant_memory_sku(); + printk(BIOS_DEBUG, "Detected MEMORY_ID = %d\n", spd_idx); + mem_cfg->MemorySpdPtr00 = (uintptr_t)mainboard_find_spd_data(spd_idx); + switch (spd_idx) { + case 1: case 3: case 7: case 11: case 14: + printk(BIOS_DEBUG, "Detected single channel\n"); + break; + default: + printk(BIOS_DEBUG, "Detected dual channel\n"); + mem_cfg->MemorySpdPtr10 = mem_cfg->MemorySpdPtr00; + break; + } +} diff --git a/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/overridetree.cb b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/overridetree.cb new file mode 100644 index 0000000000..1ef139c8f5 --- /dev/null +++ b/src/mainboard/lenovo/sklkbl_thinkpad/variants/x280/overridetree.cb @@ -0,0 +1,85 @@ +# SPDX-License-Identifier: GPL-2.0-only + +chip soc/intel/skylake + device domain 0 on + device ref south_xhci on + register "usb2_ports" = "{ + [0] = USB2_PORT_MID(OC0), // JUSB1 (USB-A always on) + [1] = USB2_PORT_MID(OC1), // JUSB2 (USB-A) + [2] = USB2_PORT_MID(OC_SKIP), // JFPR (smartcard slot) + [3] = USB2_PORT_MID(OC_SKIP), // JUSBC (USB docking station) + [4] = USB2_PORT_MID(OC_SKIP), // JIRCAM (IR camera) + [5] = USB2_PORT_MID(OC_SKIP), // JWWAN (M.2 WWAN USB) + [6] = USB2_PORT_MID(OC_SKIP), // JWLAN (M.2 WLAN USB) + [7] = USB2_PORT_MID(OC_SKIP), // JCAM (webcam) + [8] = USB2_PORT_MID(OC_SKIP), // JFPR (fingerprint reader) + [9] = USB2_PORT_MID(OC_SKIP), // JLCD (touch panel) + }" + register "usb3_ports" = "{ + [0] = USB3_PORT_DEFAULT(OC0), // JUSB1 (USB-A always on) + [1] = USB3_PORT_DEFAULT(OC1), // JUSB2 (USB-A) + [2] = USB3_PORT_DEFAULT(OC_SKIP), // JSD (SD card reader) + [3] = USB3_PORT_DEFAULT(OC_SKIP), // JUSB3 (USB docking station) + }" + end + + # PCIe + # PCIe Controller 1 - 1x2 + 2x1 + # PCIE 1-2 - RP1 - TB - CLKOUT0 - CLKREQ0 + # PCIE 3 - RP3 - WLAN - CLKOUT1 - CLKREQ1 + # PCIE 4 - GbE - GbE - CLKOUT2 - CLKREQ2 + # PCIe Controller 2 - 1x4 + # PCIE 5-8 - RP5 - NVMe - CLKOUT3 - CLKREQ3 + # PCIe Controller 3 - 4x1 + # PCIE 12 - RP9 - WWAN - CLKOUT5 - CLKREQ5 + + # TB - x2 + device ref pcie_rp1 on + register "PcieRpClkReqSupport[0]" = "true" + register "PcieRpClkReqNumber[0]" = "0" + register "PcieRpClkSrcNumber[0]" = "0" + register "PcieRpAdvancedErrorReporting[0]" = "true" + register "PcieRpHotPlug[0]" = "true" + end + + # M.2 WLAN x1 + device ref pcie_rp3 on + register "PcieRpClkReqSupport[2]" = "true" + register "PcieRpClkReqNumber[2]" = "1" + register "PcieRpClkSrcNumber[2]" = "1" + register "PcieRpAdvancedErrorReporting[2]" = "true" + register "PcieRpLtrEnable[2]" = "true" + smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X" + end + + # Ethernet (clobbers RP4) + device ref gbe on + register "LanClkReqSupported" = "true" + register "LanClkReqNumber" = "2" + register "PcieRpClkReqNumber[3]" = "2" + register "PcieRpClkSrcNumber[3]" = "2" + register "EnableLanLtr" = "true" + register "EnableLanK1Off" = "true" + end + + # M.2 2280 SSD - x4 (RP9) + device ref pcie_rp5 on + register "PcieRpClkReqSupport[4]" = "true" + register "PcieRpClkReqNumber[4]" = "3" + register "PcieRpClkSrcNumber[4]" = "3" + register "PcieRpAdvancedErrorReporting[4]" = "true" + register "PcieRpLtrEnable[4]" = "true" + smbios_slot_desc "SlotTypeM2Socket3" "SlotLengthOther" "M.2/M 2280" "SlotDataBusWidth4X" + end + + # M.2 WLAN x1 + device ref pcie_rp9 on + register "PcieRpClkReqSupport[8]" = "true" + register "PcieRpClkReqNumber[8]" = "5" + register "PcieRpClkSrcNumber[8]" = "5" + register "PcieRpAdvancedErrorReporting[8]" = "true" + register "PcieRpLtrEnable[8]" = "true" + smbios_slot_desc "SlotTypeM2Socket1_DP" "SlotLengthOther" "M.2/A 2230" "SlotDataBusWidth1X" + end + end +end