From 0a867b397171d138f5688a7f7f486b15323c5970 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Tue, 16 Sep 2025 09:24:20 +0200 Subject: [PATCH] acpi/ivrs: Fill second EFR image value MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Based on AMD doc #48882 PUB Rev 3.10 [1]. Now, the IVHD type 11h and 40h have a second 64bit EFR value that should be filled with IOMMU MMIO offset 0x1A0 register value if EFR is supported. [1] https://docs.amd.com/v/u/en-US/48882_IOMMU Change-Id: I0da79bed8994671c651328cd7a29d9480a122528 Signed-off-by: Michał Żygowski Reviewed-on: https://review.coreboot.org/c/coreboot/+/89200 Tested-by: build bot (Jenkins) Reviewed-by: Matt DeVillier Reviewed-by: Alicja Michalska Reviewed-by: Maximilian Brune --- src/include/acpi/acpi.h | 3 ++- src/include/acpi/acpi_ivrs.h | 3 ++- src/soc/amd/common/block/acpi/ivrs.c | 4 ++++ 3 files changed, 8 insertions(+), 2 deletions(-) diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index ca1ec7d894..87c99a1eb3 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -595,7 +595,8 @@ typedef struct acpi_ivrs_ivhd_11 { struct ivhd11_iommu_attr iommu_attributes; uint32_t efr_reg_image_low; uint32_t efr_reg_image_high; - uint32_t reserved[2]; + uint32_t efr_reg_image2_low; + uint32_t efr_reg_image2_high; uint8_t entry[]; } __packed acpi_ivrs_ivhd11_t; diff --git a/src/include/acpi/acpi_ivrs.h b/src/include/acpi/acpi_ivrs.h index ad86e6a2f3..3efd654e53 100644 --- a/src/include/acpi/acpi_ivrs.h +++ b/src/include/acpi/acpi_ivrs.h @@ -200,7 +200,8 @@ typedef struct acpi_ivrs_ivhd_40 { uint32_t iommu_attributes; uint32_t efr_reg_image_low; uint32_t efr_reg_image_high; - uint32_t reserved[2]; + uint32_t efr_reg_image2_low; + uint32_t efr_reg_image2_high; uint8_t entry[]; } __packed acpi_ivrs_ivhd40_t; diff --git a/src/soc/amd/common/block/acpi/ivrs.c b/src/soc/amd/common/block/acpi/ivrs.c index 451a6c0879..2301158a0a 100644 --- a/src/soc/amd/common/block/acpi/ivrs.c +++ b/src/soc/amd/common/block/acpi/ivrs.c @@ -223,6 +223,8 @@ static unsigned long acpi_fill_ivrs40(unsigned long current, acpi_ivrs_ivhd_t *i if (pci_read_config32(iommu_dev, ivhd_40->capability_offset) & EFR_FEATURE_SUP) { ivhd_40->efr_reg_image_low = read32p(ivhd_40->iommu_base_low + 0x30); ivhd_40->efr_reg_image_high = read32p(ivhd_40->iommu_base_low + 0x34); + ivhd_40->efr_reg_image2_low = read32p(ivhd_40->iommu_base_low + 0x1a0); + ivhd_40->efr_reg_image2_high = read32p(ivhd_40->iommu_base_low + 0x1a4); } current += sizeof(acpi_ivrs_ivhd40_t); @@ -282,6 +284,8 @@ static unsigned long acpi_fill_ivrs11(unsigned long current, acpi_ivrs_ivhd_t *i if (pci_read_config32(iommu_dev, ivhd_11->capability_offset) & EFR_FEATURE_SUP) { ivhd_11->efr_reg_image_low = read32p(ivhd_11->iommu_base_low + 0x30); ivhd_11->efr_reg_image_high = read32p(ivhd_11->iommu_base_low + 0x34); + ivhd_11->efr_reg_image2_low = read32p(ivhd_11->iommu_base_low + 0x1a0); + ivhd_11->efr_reg_image2_high = read32p(ivhd_11->iommu_base_low + 0x1a4); } current += sizeof(acpi_ivrs_ivhd11_t);