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rk3288: DDR3 reboot test fail

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the reset single request 200us, we set the DDR_PUBL_PTR2 BIT0~BIT16 to
generate this single, when DDR run the 666Mhz, we calculate the value 0x20850,
exceed 0x1ffff(max value support by 17bit), so only 0x850 work, it only
generate 3.5us reset single, whitch don't meet the standard. So, now we set to maximun
when the value overflow, the reset single is 196us when ddr run the 666MHz.

BUG=chrome-os-partner:34875
TEST=loop reboot
BRANCH=veyron

Change-Id: I9b410e1605c87f12a5ca96ead12f8527ca4f417f
Signed-off-by: jinkun.hong <jinkun.hong@rock-chips.com>
Reviewed-on: https://chromium-review.googlesource.com/242175
Reviewed-by: Julius Werner <jwerner@chromium.org>
(cherry picked from commit 767a4a3cb8dff47cb15064d335b78ffa5815914d)
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/243124
This commit is contained in:
jinkun.hong 2015-01-21 16:03:43 +08:00 • committed by ChromeOS Commit Bot
commit 0904ac0437
1 changed files with 2 additions and 2 deletions
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4
src/soc/rockchip/rk3288/sdram.c
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@ -639,6 +639,7 @@ static void pctl_cfg(u32 channel,
static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params)
{
u32 i;
u32 dinit2 = div_round_up(sdram_params->ddr_freq/MHz * 200000, 1000);
struct rk3288_ddr_publ_regs *ddr_publ_regs = rk3288_ddr_publ[channel];
struct rk3288_msch_regs *msch_regs = rk3288_msch[channel];
@ -660,8 +661,7 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params)
* 500000, 1000))
| PRT_DINIT1(div_round_up(sdram_params->ddr_freq/MHz
* 400, 1000)), &ddr_publ_regs->ptr[1]);
writel(PRT_DINIT2(div_round_up(sdram_params->ddr_freq/MHz
* 200000, 1000))
writel(PRT_DINIT2(MIN(dinit2, 0x1ffff))
| PRT_DINIT3(div_round_up(sdram_params->ddr_freq/MHz
* 1000, 1000)), &ddr_publ_regs->ptr[2]);