From 0904ac0437e049231eafefb50b57c0416eab6c3e Mon Sep 17 00:00:00 2001 From: "jinkun.hong" Date: Wed, 21 Jan 2015 16:03:43 +0800 Subject: [PATCH] rk3288: DDR3 reboot test fail the reset single request 200us, we set the DDR_PUBL_PTR2 BIT0~BIT16 to generate this single, when DDR run the 666Mhz, we calculate the value 0x20850, exceed 0x1ffff(max value support by 17bit), so only 0x850 work, it only generate 3.5us reset single, whitch don't meet the standard. So, now we set to maximun when the value overflow, the reset single is 196us when ddr run the 666MHz. BUG=chrome-os-partner:34875 TEST=loop reboot BRANCH=veyron Change-Id: I9b410e1605c87f12a5ca96ead12f8527ca4f417f Signed-off-by: jinkun.hong Reviewed-on: https://chromium-review.googlesource.com/242175 Reviewed-by: Julius Werner (cherry picked from commit 767a4a3cb8dff47cb15064d335b78ffa5815914d) Signed-off-by: Julius Werner Reviewed-on: https://chromium-review.googlesource.com/243124 --- src/soc/rockchip/rk3288/sdram.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/rockchip/rk3288/sdram.c b/src/soc/rockchip/rk3288/sdram.c index 5a158adb72..d330f99d6e 100644 --- a/src/soc/rockchip/rk3288/sdram.c +++ b/src/soc/rockchip/rk3288/sdram.c @@ -639,6 +639,7 @@ static void pctl_cfg(u32 channel, static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) { u32 i; + u32 dinit2 = div_round_up(sdram_params->ddr_freq/MHz * 200000, 1000); struct rk3288_ddr_publ_regs *ddr_publ_regs = rk3288_ddr_publ[channel]; struct rk3288_msch_regs *msch_regs = rk3288_msch[channel]; @@ -660,8 +661,7 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params) * 500000, 1000)) | PRT_DINIT1(div_round_up(sdram_params->ddr_freq/MHz * 400, 1000)), &ddr_publ_regs->ptr[1]); - writel(PRT_DINIT2(div_round_up(sdram_params->ddr_freq/MHz - * 200000, 1000)) + writel(PRT_DINIT2(MIN(dinit2, 0x1ffff)) | PRT_DINIT3(div_round_up(sdram_params->ddr_freq/MHz * 1000, 1000)), &ddr_publ_regs->ptr[2]);