exynos5420/kirby: necessary updates for DRAM

This updates DRAM usage for Kirby so that we can actually
use the available 3.5GB:

- The chips on Kirby have 16 row address lines.
- CONFIG_DRAM_SIZE_MB should be 3584 (4096-512).
- We use 2 DMC channels on Kirby (each with 2GB).

Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=chrome-os-partner:22144
BRANCH=none
TEST=built and booted (sorta) on Kirby, mem test succeeds

Change-Id: I86d1a96d0d1a028587f7655f8de5a2e52165e9d2
Reviewed-on: https://chromium-review.googlesource.com/167489
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>

src/cpu/samsung/exynos5420/setup.h

@@ -136,6 +136,7 @@ struct exynos5_phy_control;
 #define DMC_MEMCONFIGx_CHIP_COL_10              (3 << 8)
 #define DMC_MEMCONFIGx_CHIP_ROW_14              (2 << 4)
 #define DMC_MEMCONFIGx_CHIP_ROW_15              (3 << 4)
+#define DMC_MEMCONFIGx_CHIP_ROW_16              (4 << 4)
 #define DMC_MEMCONFIGx_CHIP_BANK_8              (3 << 0)
 
 #define DMC_MEMBASECONFIGx_CHIP_BASE(x)         (x << 16)

src/mainboard/google/kirby/Kconfig

@@ -43,9 +43,8 @@ config MAINBOARD_PART_NUMBER
 
 config DRAM_SIZE_MB
 	int
-	# FIXME(dhendrix): This should be 4096, but due to DRAM
-	# issues it seems only <2GB is stable.
-	default 2048
+	# 4096MB minus 512MB due to address space limitation
+	default 3584
 
 config EC_GOOGLE_CHROMEEC_SPI_BUS
 	hex

src/mainboard/google/kirby/memory.c

@@ -66,7 +66,9 @@ const struct mem_timings mem_timings = {
 
 		.rd_fetch = 0x3,
 
-		.zq_mode_dds = 0x6,
+		/* SLSI recommended using 30-ohm drive strength instead of
+		 * 34-ohm suggested by the SDRAM datasheet. */
+		.zq_mode_dds = 0x7,
 		.zq_mode_term = 0x1,
 		.zq_mode_noterm = 1,
 
@@ -99,7 +101,7 @@ const struct mem_timings mem_timings = {
 		.membaseconfig0 = (0x10 << 16) | DMC_CHIP_MASK_2GB,
 		.memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
 			DMC_MEMCONFIGx_CHIP_COL_10 |
-			DMC_MEMCONFIGx_CHIP_ROW_15 |
+			DMC_MEMCONFIGx_CHIP_ROW_16 |
 			DMC_MEMCONFIGx_CHIP_BANK_8,
 		.prechconfig_tp_cnt = 0xff,
 		.dpwrdn_cyc = 0xff,
@@ -110,7 +112,7 @@ const struct mem_timings mem_timings = {
 			DMC_CONCONTROL_EMPTY_DISABLE |
 			DMC_CONCONTROL_AREF_EN_DISABLE |
 			DMC_CONCONTROL_IO_PD_CON_DISABLE,
-		.dmc_channels = 1,
+		.dmc_channels = 2,
 		.chips_per_channel = 1,
 		.chips_to_configure = 1,
 		.send_zq_init = 1,