erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

exynos5420/pit/kirby: re-factor membaseconfig0/1 usage

Browse source 
membaseconfig0/1 are utterly dependent on the mainboard's particular
DRAM setup. This defines their values in the mem_timings struct for
pit and kirby.

Signed-off-by: David Hendricks <dhendrix@chromium.org>
BUG=none
BRANCH=none
TEST=booted on pit, ran /usr/local/opt/punybench/bin/memcpy_test -b,
tested on kirby in follow-up patch

Change-Id: Ifd782d1229b2418f8ddbf0bcb3f45cc828ac34b0
Reviewed-on: https://chromium-review.googlesource.com/167488
Commit-Queue: David Hendricks <dhendrix@chromium.org>
Tested-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: ron minnich <rminnich@chromium.org>
This commit is contained in:
David Hendricks 2013-08-29 14:05:21 -07:00 • committed by Caroline Tice
commit 80eebd5bc0
4 changed files with 29 additions and 24 deletions
Download patch file Download diff file Expand all files Collapse all files

22
src/cpu/samsung/exynos5420/dmc_init_ddr3.c
View file

@ -145,21 +145,15 @@ int ddr3_mem_ctrl_init(struct mem_timings *mem, int interleave_size, int reset)
update_reset_dll(drex0, DDR_MODE_DDR3);
update_reset_dll(drex1, DDR_MODE_DDR3);
/* Set Base Address:
* 0x2000_0000 ~ 0x5FFF_FFFF
* 0x6000_0000 ~ 0x9FFF_FFFF
*/
/* MEMBASECONFIG0 */
val = DMC_MEMBASECONFIGx_CHIP_BASE(DMC_CHIP_BASE_0) |
DMC_MEMBASECONFIGx_CHIP_MASK(DMC_CHIP_MASK);
writel(val, &tzasc0->membaseconfig0);
writel(val, &tzasc1->membaseconfig0);
/* MEMBASECONFIG0 (CS0) */
writel(mem->membaseconfig0, &tzasc0->membaseconfig0);
writel(mem->membaseconfig0, &tzasc1->membaseconfig0);
/* MEMBASECONFIG1 */
val = DMC_MEMBASECONFIGx_CHIP_BASE(DMC_CHIP_BASE_1) |
DMC_MEMBASECONFIGx_CHIP_MASK(DMC_CHIP_MASK);
writel(val, &tzasc0->membaseconfig1);
writel(val, &tzasc1->membaseconfig1);
/* MEMBASECONFIG1 (CS1) */
if (mem->chips_per_channel == 2) {
writel(mem->membaseconfig1, &tzasc0->membaseconfig1);
writel(mem->membaseconfig1, &tzasc1->membaseconfig1);
}
/* Memory Channel Inteleaving Size
* Exynos5420 Channel interleaving = 128 bytes

15
src/cpu/samsung/exynos5420/setup.h
View file

@ -767,15 +767,12 @@ struct exynos5_phy_control;
#define DPWRDN_EN (1 << 1)
#define DSREF_EN (1 << 5)
/* As we use channel interleaving, therefore value of the base address
* register must be set as half of the bus base address
* RAM start addess is 0x2000_0000 which means chip_base is 0x20, so
* we need to set half 0x10 to the membaseconfigx registers
* see exynos5420 UM section 17.17.3.21 for more
*/
#define DMC_CHIP_BASE_0 0x10
#define DMC_CHIP_BASE_1 0x50
#define DMC_CHIP_MASK 0x7C0
/* AXI base address mask */
#define DMC_CHIP_MASK_256MB 0x7f0
#define DMC_CHIP_MASK_512MB 0x7e0
#define DMC_CHIP_MASK_1GB 0x7c0
#define DMC_CHIP_MASK_2GB 0x780
#define DMC_CHIP_MASK_4GB 0x700
#define MEMBASECONFIG_CHIP_MASK_VAL 0x7E0
#define MEMBASECONFIG_CHIP_MASK_OFFSET 0

7
src/mainboard/google/kirby/memory.c
View file

@ -90,6 +90,13 @@ const struct mem_timings mem_timings = {
DMC_MEMCONTROL_BL_8 |
DMC_MEMCONTROL_PZQ_DISABLE |
DMC_MEMCONTROL_MRR_BYTE_7_0,
/*
* For channel interleaving, the chip_base needs to be set to
* half the bus address. So for a base address of 0x2000_0000,
* the chip_base value is 0x20 without interleaving and 0x10
* with channel interleaving. See note in section 17.14.
*/
.membaseconfig0 = (0x10 << 16) | DMC_CHIP_MASK_2GB,
.memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
DMC_MEMCONFIGx_CHIP_COL_10 |
DMC_MEMCONFIGx_CHIP_ROW_15 |

7
src/mainboard/google/pit/memory.c
View file

@ -90,6 +90,13 @@ const struct mem_timings mem_timings = {
DMC_MEMCONTROL_BL_8 |
DMC_MEMCONTROL_PZQ_DISABLE |
DMC_MEMCONTROL_MRR_BYTE_7_0,
/*
* For channel interleaving, the chip_base needs to be set to
* half the bus address. So for a base address of 0x2000_0000,
* the chip_base value is 0x20 without interleaving and 0x10
* with channel interleaving. See note in section 17.14.
*/
.membaseconfig0 = (0x10 << 16) | DMC_CHIP_MASK_1GB,
.memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
DMC_MEMCONFIGx_CHIP_COL_10 |
DMC_MEMCONFIGx_CHIP_ROW_15 |