From 0416ac98297b6850b41bbbe12a2bbfa41844490b Mon Sep 17 00:00:00 2001 From: Tongtong Pan Date: Wed, 12 Nov 2025 14:56:20 +0800 Subject: [PATCH] mb/google/var/fatcat/lapis: Modify type-A USB3 port0/1 tx_de_emp Fix USB 3.2 Type-A port0/1 Tx compliance failures in EA test - De-emphasis test failed: Actual value = 0.000000 dB, requirement: -7.0 dB <= value <= -2.1 dB - Preshoot test failed: Actual value = 0.000000 dB, requirement: 1.2 dB <= value <= 3.2 dB Set Type-A USB3 port0/1 tx_de_emp to 0x4 for signal integrity BUG=b/451560515 TEST=build FW and check Type-A USB3 port0/port1 RX pass in EA test Change-Id: I1a563fbc27d2dac8b57a62b7bfded73e1a6732cf Signed-off-by: Tongtong Pan Reviewed-on: https://review.coreboot.org/c/coreboot/+/90004 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/google/fatcat/variants/lapis/overridetree.cb | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb index 299483d626..3d7e53aba5 100644 --- a/src/mainboard/google/fatcat/variants/lapis/overridetree.cb +++ b/src/mainboard/google/fatcat/variants/lapis/overridetree.cb @@ -80,8 +80,8 @@ chip soc/intel/pantherlake register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Discrete Bluetooth - register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 x1 Type-A Con #1 (MB)/ - register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # USB3.2 x1 Type-A Con #2 (DB)/ + register "usb3_ports[0]" = "USB3_PORT_TX_CFG(OC_SKIP, 0x4)" # USB3.2 x1 Type-A Con #1 (MB)/ + register "usb3_ports[1]" = "USB3_PORT_TX_CFG(OC_SKIP, 0x4)" # USB3.2 x1 Type-A Con #2 (DB)/ register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)" register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC_SKIP)"