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Fix breakage of k8 targets caused by r1085. Thanks to Myles Watson for

Browse source 
tracking down the offending commit.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>



git-svn-id: svn://coreboot.org/repository/coreboot-v3@1088 f3766cd6-281f-0410-b1cd-43a5c92072e9
This commit is contained in:
Corey Osgood 2008-12-30 07:02:52 +00:00
commit 034ea33797
6 changed files with 9 additions and 4 deletions
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2
arch/x86/amd/k8/stage1.c
View file

@ -35,7 +35,7 @@
*/
void set_init_ram_access(void)
{
set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, MTRR_TYPE_WRBACK);
stage1_set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, MTRR_TYPE_WRBACK);
}
/**

6
arch/x86/stage1_mtrr.c
View file

@ -25,7 +25,7 @@ void disable_var_mtrr(unsigned int reg)
wrmsr(MTRRphysMask_MSR(reg), zero);
}
void set_var_mtrr(
void stage1_set_var_mtrr(
unsigned long reg, unsigned long base, unsigned long size, unsigned long type)
{
@ -63,7 +63,7 @@ void cache_cbmem(int type)
{
/* Enable caching for 0 - 1MB using variable mtrr */
disable_cache();
set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, type);
stage1_set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, type);
enable_cache();
}
@ -98,7 +98,7 @@ void do_early_mtrr_init(const unsigned long *mtrr_msrs)
/* enable write through caching so we can do execute in place
* on the flash rom.
*/
set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
stage1_set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
#endif
#endif

2
include/arch/x86/mtrr.h
View file

@ -35,6 +35,8 @@
void x86_setup_var_mtrrs(unsigned address_bits);
void x86_setup_mtrrs(unsigned address_bits);
int x86_mtrr_check(void);
void stage1_set_var_mtrr(unsigned long reg, unsigned long base,
unsigned long size, unsigned long type);
#endif

1
mainboard/amd/dbm690t/Makefile
View file

@ -26,6 +26,7 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
$(src)/arch/x86/amd/model_fxx/stage1.c \
$(src)/northbridge/amd/k8/get_nodes.c \
$(src)/northbridge/amd/k8/libstage1.c \
$(src)/arch/x86/stage1_mtrr.c
INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
$(src)/northbridge/amd/k8/raminit.c \

1
mainboard/amd/serengeti/Makefile
View file

@ -30,6 +30,7 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
$(src)/southbridge/amd/amd8111/stage1_smbus.c \
$(src)/southbridge/amd/amd8111/stage1_ctrl.c \
$(src)/southbridge/amd/amd8111/stage1_enable_rom.c \
$(src)/arch/x86/stage1_mtrr.c
STAGE0_DYNAMIC_SRC := $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c

1
mainboard/gigabyte/m57sli/Makefile
View file

@ -29,6 +29,7 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \
$(src)/northbridge/amd/k8/libstage1.c \
$(src)/southbridge/nvidia/mcp55/stage1_smbus.c \
$(src)/southbridge/nvidia/mcp55/stage1_enable_rom.c \
$(src)/arch/x86/stage1_mtrr.c
STAGE0_DYNAMIC_SRC := $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c