From 034ea337970ac05c34c706c3efc30416f0f50559 Mon Sep 17 00:00:00 2001 From: Corey Osgood Date: Tue, 30 Dec 2008 07:02:52 +0000 Subject: [PATCH] Fix breakage of k8 targets caused by r1085. Thanks to Myles Watson for tracking down the offending commit. Signed-off-by: Corey Osgood Acked-by: Peter Stuge git-svn-id: svn://coreboot.org/repository/coreboot-v3@1088 f3766cd6-281f-0410-b1cd-43a5c92072e9 --- arch/x86/amd/k8/stage1.c | 2 +- arch/x86/stage1_mtrr.c | 6 +++--- include/arch/x86/mtrr.h | 2 ++ mainboard/amd/dbm690t/Makefile | 1 + mainboard/amd/serengeti/Makefile | 1 + mainboard/gigabyte/m57sli/Makefile | 1 + 6 files changed, 9 insertions(+), 4 deletions(-) diff --git a/arch/x86/amd/k8/stage1.c b/arch/x86/amd/k8/stage1.c index 0bed559dc2..b9ce84e95d 100644 --- a/arch/x86/amd/k8/stage1.c +++ b/arch/x86/amd/k8/stage1.c @@ -35,7 +35,7 @@ */ void set_init_ram_access(void) { - set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, MTRR_TYPE_WRBACK); + stage1_set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, MTRR_TYPE_WRBACK); } /** diff --git a/arch/x86/stage1_mtrr.c b/arch/x86/stage1_mtrr.c index 035f06fd2a..b8938ed527 100644 --- a/arch/x86/stage1_mtrr.c +++ b/arch/x86/stage1_mtrr.c @@ -25,7 +25,7 @@ void disable_var_mtrr(unsigned int reg) wrmsr(MTRRphysMask_MSR(reg), zero); } -void set_var_mtrr( +void stage1_set_var_mtrr( unsigned long reg, unsigned long base, unsigned long size, unsigned long type) { @@ -63,7 +63,7 @@ void cache_cbmem(int type) { /* Enable caching for 0 - 1MB using variable mtrr */ disable_cache(); - set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, type); + stage1_set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, type); enable_cache(); } @@ -98,7 +98,7 @@ void do_early_mtrr_init(const unsigned long *mtrr_msrs) /* enable write through caching so we can do execute in place * on the flash rom. */ - set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK); + stage1_set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK); #endif #endif diff --git a/include/arch/x86/mtrr.h b/include/arch/x86/mtrr.h index 61568edeb6..aedeca064a 100644 --- a/include/arch/x86/mtrr.h +++ b/include/arch/x86/mtrr.h @@ -35,6 +35,8 @@ void x86_setup_var_mtrrs(unsigned address_bits); void x86_setup_mtrrs(unsigned address_bits); int x86_mtrr_check(void); +void stage1_set_var_mtrr(unsigned long reg, unsigned long base, + unsigned long size, unsigned long type); #endif diff --git a/mainboard/amd/dbm690t/Makefile b/mainboard/amd/dbm690t/Makefile index b81f8c8b3f..2690625c0a 100644 --- a/mainboard/amd/dbm690t/Makefile +++ b/mainboard/amd/dbm690t/Makefile @@ -26,6 +26,7 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \ $(src)/arch/x86/amd/model_fxx/stage1.c \ $(src)/northbridge/amd/k8/get_nodes.c \ $(src)/northbridge/amd/k8/libstage1.c \ + $(src)/arch/x86/stage1_mtrr.c INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \ $(src)/northbridge/amd/k8/raminit.c \ diff --git a/mainboard/amd/serengeti/Makefile b/mainboard/amd/serengeti/Makefile index 7c155c2510..332c7cb343 100644 --- a/mainboard/amd/serengeti/Makefile +++ b/mainboard/amd/serengeti/Makefile @@ -30,6 +30,7 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \ $(src)/southbridge/amd/amd8111/stage1_smbus.c \ $(src)/southbridge/amd/amd8111/stage1_ctrl.c \ $(src)/southbridge/amd/amd8111/stage1_enable_rom.c \ + $(src)/arch/x86/stage1_mtrr.c STAGE0_DYNAMIC_SRC := $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c diff --git a/mainboard/gigabyte/m57sli/Makefile b/mainboard/gigabyte/m57sli/Makefile index db2a404429..db9c0224ce 100644 --- a/mainboard/gigabyte/m57sli/Makefile +++ b/mainboard/gigabyte/m57sli/Makefile @@ -29,6 +29,7 @@ STAGE0_MAINBOARD_SRC := $(src)/lib/clog2.c \ $(src)/northbridge/amd/k8/libstage1.c \ $(src)/southbridge/nvidia/mcp55/stage1_smbus.c \ $(src)/southbridge/nvidia/mcp55/stage1_enable_rom.c \ + $(src)/arch/x86/stage1_mtrr.c STAGE0_DYNAMIC_SRC := $(obj)/mainboard/$(MAINBOARDDIR)/option_table.c