erebion/coreboot
1
0
Fork 0
Code Issues Pull requests Projects Releases Packages Wiki Activity Actions

mb/google/brya/var/nova: Configure scaler I2C GPIOs

Browse source 
According to schematics, add GPP_H4/H5 configuration for scaler I2C pins (PCH_I2C_SCALER_SDA/SDL).

BUG=b:358439747
TEST=emerge-constitution coreboot chromeos-bootimage. Build successfully and boot to verify I2C.

Change-Id: Id831f594d6a57ed10867ae5ba05ae98c90ac7d9b
Signed-off-by: Kenneth Chan <kenneth.chan@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84091
Reviewed-by: David Wu <david_wu@quanta.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
This commit is contained in:
Kenneth Chan 2024-08-26 11:14:56 +08:00 • committed by Felix Held
commit 00610d57fa
1 changed files with 4 additions and 0 deletions
Download patch file Download diff file Expand all files Collapse all files

4
src/mainboard/google/brya/variants/nova/gpio.c
View file

@ -91,6 +91,10 @@ static const struct pad_config override_gpio_table[] = {
/* F16 : GSXCLK ==> MEM_STRAP_0 */
PAD_CFG_GPI_LOCK(GPP_F16, NONE, LOCK_CONFIG),
/* H4 : I2C0_SDA ==> PCH_I2C_SCALER_SDA */
PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG),
/* H5 : I2C0_SCL ==> PCH_I2C_SCALER_SCL */
PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG),
/* H12 : I2C7_SDA ==> NC */
PAD_NC_LOCK(GPP_H12, NONE, LOCK_CONFIG),
/* H13 : I2C7_SCL ==> NC */