Lijian Zhao ffe4aededf mb/google/sarien: Enable LAN clock source usage ... FSP defined a special clock source usage 0x70 for PCH LAN device, update that to google sarien platform. BUG=b:120003760 TEST=Boot up into OS, ethernet able to be listed in ifconfig. Change-Id: I9f945be4f0ce15470ab53f44e60143f3fd0fddf8 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/c/30100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Subrata Banik <subrata.banik@intel.com> Reviewed-by: Duncan Laurie <dlaurie@chromium.org>		2018-12-09 09:29:28 +00:00
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acpi
arch	riscv: fix non-SMP support	2018-12-07 11:37:53 +00:00
commonlib	src: Remove duplicated round up function	2018-11-29 12:17:45 +00:00
console
cpu	cpu/x86/pae: Fix pointer casts	2018-12-05 16:57:15 +00:00
device	arch/power8: Rename to ppc64	2018-11-30 20:02:17 +00:00
drivers	drivers/i2c/designware: Add soc_clock entry for 216MHz	2018-12-07 11:18:55 +00:00
ec	lenovo/h8,thinkpads: Re-do USB Always On	2018-12-06 11:59:22 +00:00
include	smmstore: make smmstore's SMM handler code follow everything else	2018-12-05 13:31:22 +00:00
lib	cbfs: Alert if something goes wrong in cbfs_boot_locate()	2018-12-07 11:34:54 +00:00
mainboard	mb/google/sarien: Enable LAN clock source usage	2018-12-09 09:29:28 +00:00
northbridge	nb/intel/gm45: Make fetching the blc_pwm freq global	2018-12-03 13:03:13 +00:00
security	tss: implement tlcl_save_state	2018-11-28 18:32:59 +00:00
soc	soc/intel/apollolake: Print ME version on exit of BS_DEV_INIT stage	2018-12-07 11:38:30 +00:00
southbridge	sb/amd/pi/hudson: Fix UART address math	2018-12-07 11:34:13 +00:00
superio
vendorcode
Kconfig