coreboot/src/soc
Subrata Banik ff9104eae3 soc/intel/icelake: Clear PMCON status bits
This patch ports CB:31902 changes from CNL to ICL.

The prev_sleep_state value was showing 5 even after warm reboot, once the
SUS_PWR_FLR bit is being set. This bit was not being cleared.
Hence clearing the PMCON status bits.

Change-Id: Ia07aa17b4491216a277c36edfe6ed2aa489287c6
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32503
Reviewed-by: Rizwan Qureshi <rizwan.qureshi@intel.com>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
2019-05-02 06:02:40 +00:00
..
amd soc/{amd,intel}/chip: Use local include for chip.h 2019-04-26 16:49:13 +00:00
cavium soc/cavium/common/bootblock: Remove unused variables 2019-04-25 15:55:27 +00:00
imgtec arch/mips: Fix <arch/mmio.h> prototypes 2019-03-22 12:18:41 +00:00
intel soc/intel/icelake: Clear PMCON status bits 2019-05-02 06:02:40 +00:00
mediatek vboot: refactor OPROM code 2019-04-30 21:47:25 +00:00
nvidia vboot: refactor OPROM code 2019-04-30 21:47:25 +00:00
qualcomm vboot: refactor OPROM code 2019-04-30 21:47:25 +00:00
rockchip rockchip: rk3399: increase memory for fit payload. 2019-04-30 22:38:10 +00:00
samsung src: include <assert.h> when appropriate 2019-04-23 10:01:36 +00:00
sifive src/mb/sifive/hifive-unleashed: initialize Gigabit Ethernet Controller 2019-03-18 09:12:46 +00:00
ucb