coreboot/src
Ben Chuang ff17b31dfb drivers/genesyslogic/gl9755: Add driver for Genesys Logic GL9755
The device is a PCIe Gen2 to SD 4.0 card reader controller to be
used in the Chromebook. The datasheet name is GL9755S and the revision
is 05.

The patch sets LTR value.

Signed-off-by: Ben Chuang <benchuanggli@gmail.com>
Change-Id: I16048dde348be248c748d50ca4a8a62c8a781430
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45062
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
2020-09-18 15:49:15 +00:00
..
acpi acpi: Correct sizes for ACPI data fields 2020-09-15 13:41:58 +00:00
arch
commonlib util/cbfstool: extend includes in commonlib 2020-09-14 07:10:53 +00:00
console ec/system76: Add console support 2020-09-07 21:46:34 +00:00
cpu cpu/intel/model_1067x: enable PECI 2020-09-12 10:50:33 +00:00
device src: Remove redundant <device/pnp_def.h> 2020-09-17 13:21:48 +00:00
drivers drivers/genesyslogic/gl9755: Add driver for Genesys Logic GL9755 2020-09-18 15:49:15 +00:00
ec ec/google/chromeec: Add dptc interface support 2020-09-17 06:18:59 +00:00
include drivers/genesyslogic/gl9755: Add driver for Genesys Logic GL9755 2020-09-18 15:49:15 +00:00
lib region_file_update_data_arr: Modify region_file with array of buffers 2020-09-16 16:02:54 +00:00
mainboard mb/google/volteer/eldrid: Add option to enable WiFi SAR configs 2020-09-18 15:46:26 +00:00
northbridge nb/intel/haswell: Put DMIBAR/EPBAR registers into separate files 2020-09-17 20:22:31 +00:00
security
soc soc/intel/cannonlake: add missing special function pads 2020-09-17 21:53:38 +00:00
southbridge sb/intel/lynxpoint/acpi: Do not determine PCH type at runtime 2020-09-14 07:07:12 +00:00
superio superio/nuvoton: Inline nuvoton_hwm_select_bank 2020-09-18 12:37:36 +00:00
vendorcode chromeos: Provide common watchdog reboot support in romstage 2020-09-15 01:09:38 +00:00
Kconfig