Saurabh Mishra 25d16291d4 vc/intel/fsp: Update ADL N FSP headers from v3267.01 to v3301.00 ... Update generated FSP headers for Alder Lake N from v3267.01 to v3301.00. Changes include: - FspsUpd.h: 1. Add VccInAuxImonSlope UPD 2. Update UPD Offset in FspsUpd.h BUG=b:242152105 BRANCH=None TEST=Build using "emerge-nissa intel-adlnfsp"and boot Nissa. Change-Id: I7b921e2aa467593a1c764fc554e2e83e8bb526e8 Signed-off-by: Saurabh Mishra <mishra.saurabh@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/67167 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Kangheui Won <khwon@chromium.org>		2022-09-04 16:08:32 +00:00
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amd	vc/amd/fsp/mendocino: Update DMI_T17_MEMORY_TYPE	2022-08-24 15:14:15 +00:00
cavium	rules.h: Use more consistent naming	2022-05-16 21:52:22 +00:00
eltan	cbfs/vboot: Adapt to new vb2_digest API	2022-09-02 23:51:29 +00:00
google	util/elogtool: Mark redundant boot mode event type as deprecated	2022-08-06 14:06:33 +00:00
intel	vc/intel/fsp: Update ADL N FSP headers from v3267.01 to v3301.00	2022-09-04 16:08:32 +00:00
mediatek	mb/google: Replace some strings in regulator.c	2022-07-21 10:30:57 +00:00
siemens	cbfs: Simplify load/map API names, remove type arguments	2020-12-02 22:13:17 +00:00
Makefile.inc	soc/mediatek/mt8192: initialize DRAM using vendor reference code	2021-03-08 03:15:43 +00:00