Lijian Zhao fe701ee398 soc/intel/cannonlake: Enable ISH from device ... PCH ISH enabled/disabled in FSP memory init UPD, it will be match the setting in ISH device on/off in devicetree.cb. BUG=N/A TEST=Build and pass on whiskey lake rvp platform. Change-Id: I6889634bf65e7ce5cc3e3393c57c86d622f1ac68 Signed-off-by: Lijian Zhao <lijian.zhao@intel.com> Reviewed-on: https://review.coreboot.org/29274 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com> Reviewed-by: Bora Guvendik <bora.guvendik@intel.com>		2018-11-05 09:06:49 +00:00
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apollolake	src: Remove unneeded include <arch/ioapic.h>	2018-11-05 09:01:42 +00:00
baytrail	src: Add missing include <stdint.h>	2018-10-30 09:41:08 +00:00
braswell	src: Add missing include <stdint.h>	2018-10-30 09:41:08 +00:00
broadwell	src: Add missing include <stdint.h>	2018-11-01 11:25:07 +00:00
cannonlake	soc/intel/cannonlake: Enable ISH from device	2018-11-05 09:06:49 +00:00
common	soc/intel: Enable GPIO functions in verstage	2018-11-02 16:06:53 +00:00
denverton_ns	src: Add missing include <stdint.h>	2018-11-01 11:25:07 +00:00
fsp_baytrail	src: Add missing include <stdint.h>	2018-10-30 09:41:08 +00:00
fsp_broadwell_de	src: Remove unneeded include <arch/ioapic.h>	2018-11-05 09:01:42 +00:00
icelake	src: Remove unneeded include <arch/ioapic.h>	2018-11-05 09:01:42 +00:00
quark	src: Add missing include <stdint.h>	2018-11-01 11:25:07 +00:00
skylake	src: Add missing include <stdint.h>	2018-11-01 11:25:07 +00:00
Kconfig	soc/intel/icelake: Do initial SoC commit	2018-10-26 11:20:54 +00:00