Raul E Rangel fd7ed87746 soc/amd/cezanne: Populate PCI_INTR registers ... This uses the new FSP PCI methods to pull the routing table and populate the pirq data structure. BUG=b:184766519 TEST=Boot guybrush and verify we get Got IRQ 0x1F (disabled) messages Signed-off-by: Raul E Rangel <rrangel@chromium.org> Change-Id: Ie21229cc2fb4fd5b85c0b9e933f7b43af24864b0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/52914 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Felix Held <felix-coreboot@felixheld.de>		2021-05-09 18:09:53 +00:00
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amd	soc/amd/cezanne: Populate PCI_INTR registers	2021-05-09 18:09:53 +00:00
cavium
example
intel	soc/intel/{adl,tgl,jsl}: Enable power button smi after BS_CHIPS_EXIT	2021-05-07 06:05:37 +00:00
mediatek	soc/mediatek/mt8195: Turn off L2C SRAM and reconfigure as L2 cache	2021-05-07 10:20:30 +00:00
nvidia	cbfs: Replace more instances of cbfs_boot_locate() with newer APIs	2021-03-17 08:10:20 +00:00
qualcomm	Coachz: Observe SPI_CLK voltage level is only 1.4V, need to adjust	2021-04-24 00:24:00 +00:00
rockchip	soc/rockchip/rk3399/sdram: Add channel to error message	2021-03-04 01:22:10 +00:00
samsung	commonlib/region: Turn addrspace_32bit into a more official API	2021-04-21 02:06:26 +00:00
sifive	memlayout: Store region sizes as separate symbols	2021-02-19 08:39:26 +00:00
ti	soc/ti/am335x/mmc.c: Fix memset length argument	2021-04-04 09:58:26 +00:00
ucb