Arthur Heymans fd2bb9b6bc soc/amd/*: Hook up SMBus ops to devicetree ... This removes the need for a PCI driver. Change-Id: Iab75f8c28a247f1370f4425e19cc215678bfa3e5 Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Signed-off-by: Felix Held <felix-coreboot@felixheld.de> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68140 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martin.roth@amd.corp-partner.google.com>		2022-10-14 20:18:45 +00:00
..
acpi	treewide: use is_enabled_cpu() on cycles over device list	2022-09-29 16:47:04 +00:00
arch	smbios: Add API to generate SMBIOS type 28 Temperature Probe	2022-10-06 18:36:03 +00:00
commonlib	util/elogtool: Add support for parsing CrOS diagnostics log	2022-10-14 16:06:39 +00:00
console	console/vtxprintf.c: Add <stdarg.h>	2022-10-06 17:00:25 +00:00
cpu	cpu/x86/64bit: Fix building with -jx	2022-10-12 12:04:00 +00:00
device	device/dram/ddr2: Use 'enum cb_err' instead of 'int'	2022-10-12 13:05:59 +00:00
drivers	mb/google/brya/nivviks: Enable ISH driver and firmware name	2022-10-11 14:44:06 +00:00
ec	ec/google/chromeec: Demote LPC EC error printk from ERR to SPEW	2022-10-14 16:10:23 +00:00
include	device: Drop unused ADL-N UFS PCI Device ID	2022-10-12 23:51:43 +00:00
lib	payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity	2022-10-13 19:14:57 +00:00
mainboard	mb/google/rex: Add initial fw config	2022-10-14 16:01:04 +00:00
northbridge	payloads,src: Replace ALIGN(x, a) by ALIGN_UP(x, a) for clarity	2022-10-13 19:14:57 +00:00
sbom
security	security/memory/memory.h: Add <stdbool.h>	2022-10-06 17:01:52 +00:00
soc	soc/amd/*: Hook up SMBus ops to devicetree	2022-10-14 20:18:45 +00:00
southbridge	treewide: Use 'fadt->x_pm1a_cnt_blk.addrl = fadt->pm1a_cnt_blk'	2022-10-12 14:18:44 +00:00
superio
vendorcode	vc/amd/fsp: Add Morgana FSP vendorcode	2022-10-08 20:58:58 +00:00
Kconfig	coreboot: Add support for include-what-you-use	2022-10-11 14:33:28 +00:00