Corey Osgood fcf66e3605 Enable caching for Via C7 CPUs, and also improve readability. Tested on hardware ... and seems to be working. Signed-off-by: Corey Osgood <corey.osgood@gmail.com> Acked-by: Myles Watson <mylesgw@gmail.com> git-svn-id: svn://coreboot.org/repository/coreboot-v3@1164 f3766cd6-281f-0410-b1cd-43a5c92072e9		2009-04-14 15:41:33 +00:00
..
adl	cs5536: Remove redundant enable_ide variable from ide device.	2009-01-09 18:12:08 +00:00
amd	Add AP detection to stage0 to prevent APs from re-initializing mainboard setup	2009-02-10 22:41:35 +00:00
amp	cs5536: Remove redundant enable_ide variable from ide device.	2009-01-09 18:12:08 +00:00
artecgroup	cs5536: Make NAND code optional and implement timing setting	2009-02-23 18:42:44 +00:00
emulation	This patch should serve as a porting help for other northbridges for the new resource allocator.	2008-12-31 20:00:30 +00:00
gigabyte	Add AP detection to stage0 to prevent APs from re-initializing mainboard setup	2009-02-10 22:41:35 +00:00
jetway	Enable caching for Via C7 CPUs, and also improve readability. Tested on hardware	2009-04-14 15:41:33 +00:00
kontron	last kontron commit.	2009-03-11 16:17:37 +00:00
pcengines	cs5536: Remove redundant enable_ide variable from ide device.	2009-01-09 18:12:08 +00:00
via	Kill off stage1_mtrr.c completely, and bring in mtrr.c for stage2 from v2.	2008-12-23 19:02:44 +00:00
Kconfig	Make C7/CN700 boot to memtest86, and pass that test. Booting is very slow, ~15min to get to a memtest	2008-12-17 21:17:01 +00:00