Angel Pons fcc26f54a0 soc/intel/broadwell/pch/acpi: Add PCIe register offsets ... These are present in common southbridge ACPI code, and also exist on Broadwell. Thus, add the definitions to align with common ACPI code. Change-Id: Ib0ad9da80920fe7c70986e541c50f6adccb49d0c Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46761 Reviewed-by: Nico Huber <nico.h@gmx.de> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>		2020-11-04 22:38:56 +00:00
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amd	soc/amd/common/psp: move v1-only mailbox commands to separate section	2020-11-04 19:37:42 +00:00
cavium	soc/cavium: Drop unneeded empty lines	2020-09-22 17:14:49 +00:00
example	x86: Add a minimal example SoC along with a board	2020-10-30 21:34:18 +00:00
intel	soc/intel/broadwell/pch/acpi: Add PCIe register offsets	2020-11-04 22:38:56 +00:00
mediatek	soc/mediatek/mt8192: Do dram full calibration	2020-10-29 00:30:34 +00:00
nvidia	soc/nvidia: Drop unneeded empty lines	2020-09-22 17:14:59 +00:00
qualcomm	sc7180: Fix prefill requirement and correct the fetch start check	2020-11-02 22:04:33 +00:00
rockchip	soc/rockchip/rk3288/include/soc/display.h: Add missing includes	2020-10-19 07:12:07 +00:00
samsung	src/soc/samsung: Move common headers to "common/include/soc"	2020-10-19 07:11:32 +00:00
sifive	include/console/uart: make index parameter unsigned	2020-09-12 14:59:33 +00:00
ti	include/console/uart: make index parameter unsigned	2020-09-12 14:59:33 +00:00
ucb	soc/ucb/riscv: Add chip_operations stub	2020-05-28 09:30:35 +00:00