coreboot/src/soc/intel
Kyösti Mälkki fcbbb91116 Remove MAYBE_STATIC_BSS and ENV_STAGE_HAS_BSS_SECTION
After removal of CAR_MIGRATION there are no more reasons
to carry around ENV_STAGE_HAS_BSS_SECTION=n case.

Replace 'MAYBE_STATIC_BSS' with 'static' and remove explicit
zero-initializers.

Change-Id: I14dd9f52da5b06f0116bd97496cf794e5e71bc37
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40535
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-by: Julius Werner <jwerner@chromium.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
2020-05-26 15:04:08 +00:00
..
apollolake soc/intel: Drop ABOVE_4GB_MEM_BASE_SIZE and use cpu_phys_address_size() 2020-05-14 15:06:39 +00:00
baytrail Remove MAYBE_STATIC_BSS and ENV_STAGE_HAS_BSS_SECTION 2020-05-26 15:04:08 +00:00
braswell Remove MAYBE_STATIC_BSS and ENV_STAGE_HAS_BSS_SECTION 2020-05-26 15:04:08 +00:00
broadwell soc/intel/broadwell: Use SPDX identifier 2020-05-23 21:03:35 +00:00
cannonlake cannonlake: update processor power limits configuration 2020-05-26 15:02:54 +00:00
common soc/intel/common/block: Update SA resource length to support 64 bit 2020-05-23 07:34:30 +00:00
denverton_ns src: Remove unused 'include <lib.h>' 2020-05-18 07:39:17 +00:00
icelake icelake: remove unused processor power limits configuration 2020-05-20 09:13:55 +00:00
jasperlake soc/intel/jasperlake: correct IRQ routing Jasper Lake 2020-05-26 05:55:30 +00:00
quark src: Remove leading blank lines from SPDX header 2020-05-18 07:00:27 +00:00
skylake soc/intel/skylake: Mask lower 20 bits of TOLUD and TOLM in systemagent.asl 2020-05-20 00:35:10 +00:00
tigerlake soc/intel/tigerlake: Fix wrong operation region for CPU to PCH method 2020-05-26 15:02:16 +00:00
xeon_sp src: Remove leading blank lines from SPDX header 2020-05-18 07:00:27 +00:00
Kconfig fsp2_0: Gather Kconfig declarations 2020-04-05 23:26:24 +00:00