coreboot/src
Subrata Banik fc98c0195e common/block/xhci: Get XHCI PCI ID from device/pci_ids.h
Change-Id: I33d92a173055ea18b8675c720f01dd5bc77befa3
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/19536
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
2017-05-05 23:26:10 +02:00
..
acpi src/acpi: Capitalize ACPI and SATA 2016-07-31 19:25:40 +02:00
arch arch/x86: Share storage data structures between early stages 2017-05-01 17:37:59 +02:00
commonlib commonlib: Add ID for STORAGE_DATA 2017-04-28 19:56:11 +02:00
console console: rework log level to not be reliant on ROMSTAGE_CONST 2017-04-25 18:13:56 +02:00
cpu nb/amd/amdk8: Link reset_test.c 2017-04-28 17:17:40 +02:00
device lib/edid.c: Allow use of when not NGI 2017-05-03 16:16:32 +02:00
drivers drivers/{aspeed,xgi_z9s}/Kconfig: Don't override NATIVE_VGA_USE_EDID 2017-05-03 16:19:18 +02:00
ec ec/google/chromeec: provide reboot function 2017-05-05 23:23:58 +02:00
include cr50: check if the new image needs to be enabled and act on it 2017-05-05 23:24:20 +02:00
lib lib/edid: Save the display ASCII string 2017-05-03 16:18:15 +02:00
mainboard mb/google/poppy: Add eMMC as thermal sensor 2017-05-05 23:20:48 +02:00
northbridge nb/intel/sandybridge/early_init: Use register name 2017-05-05 23:23:16 +02:00
soc common/block/xhci: Get XHCI PCI ID from device/pci_ids.h 2017-05-05 23:26:10 +02:00
southbridge sb/intel/bd82x6x/bootblock: Use register name 2017-05-05 23:22:51 +02:00
superio superio/fintek: Add support for Fintek F71808A 2017-03-27 19:19:56 +02:00
vboot vboot: Separate board name and version number in FWID with a dot 2017-04-29 01:44:10 +02:00
vendorcode cr50: check if the new image needs to be enabled and act on it 2017-05-05 23:24:20 +02:00
Kconfig cr50: check if the new image needs to be enabled and act on it 2017-05-05 23:24:20 +02:00