coreboot/src/vendorcode
York Yang fc1c1b572f intel/fsp_baytrail: add Gold3 FSP support
Baytrail Gold3 FSP adds a couple of parameters in UPD_DATA_REGION
making platform more configurable via devicetree.cb
Update the UPD_DATA_REGION structure and pass settings to FSP

Add Baytrail Gold2 and earlier FSP backward compatible, as Gold3
FSP changes UPD_DATA_REGION struct

Change-Id: Ia2d2d0595328ac771762a84da40697a3b7e900c6
Signed-off-by: York Yang <york.yang@intel.com>
Reviewed-on: http://review.coreboot.org/7334
Reviewed-by: Martin Roth <gaumless@gmail.com>
Tested-by: build bot (Jenkins)
2014-11-21 23:05:19 +01:00
..
amd AMD: Isolate AGESA and PI build environments for southbridge 2014-11-20 19:03:26 +01:00
google vboot: allow non-relocatable ramstage loading 2014-11-15 00:40:15 +01:00
intel intel/fsp_baytrail: add Gold3 FSP support 2014-11-21 23:05:19 +01:00
Kconfig AMD Steppe Eagle: Add binary PI vendorcode files 2014-08-30 19:13:45 +02:00
Makefile.inc Add Intel FSP northbridge support Sandybridge and Ivybridge 2013-12-04 18:45:13 +01:00