This is a follow-up to CL:320623 to make veyron DRAM configs uniform (except for Rialto). As discussed in chrome-os-partner:43626, the mr[3] value and ODT are set diffently for Mickey, thus the .inc files for other boards have mr[3] = 1 and ODT disabled. For cherry-picking, the change was applied for all Chromebook platforms individually rather than just src/mainboard/veyron/. BUG=none BRANCH=veyron TEST=compile tested for veyron Signed-off-by: David Hendricks <dhendrix@chromium.org> Change-Id: Iacf821645a2dcceaed1c1c42e3e1b1c312b31eab Reviewed-on: https://chromium-review.googlesource.com/322487 |
||
|---|---|---|
| .. | ||
| arch | ||
| console | ||
| cpu | ||
| device | ||
| drivers | ||
| ec | ||
| include | ||
| lib | ||
| mainboard | ||
| northbridge | ||
| soc | ||
| southbridge | ||
| superio | ||
| vendorcode | ||
| Kconfig | ||