Johnson Wang fb660c35b5 soc/mediatek/mt8188: Fix audio sampling rate ... The current clock register definition is wrong, which results in wrong audio sampling rate. Fix it by adjusting the POSTDIV registers of APLL1-APLL5. TEST=build pass BUG=b:250459803, b:250464574 Change-Id: I7a627169593f41906856777d738c6b13ff72d5a0 Signed-off-by: Johnson Wang <johnson.wang@mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/73134 Reviewed-by: Yidi Lin <yidilin@google.com> Reviewed-by: Rex-BC Chen <rex-bc.chen@mediatek.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso@google.com>		2023-02-22 03:18:17 +00:00
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common	mb/google/geralt: Init MT6359P only once in ramstage	2023-02-09 09:19:00 +00:00
mt8173	soc/mediatek: Include <gpio.h> instead of <soc/gpio.h>	2023-01-13 16:51:36 +00:00
mt8183	soc/mediatek: Include <gpio.h> instead of <soc/gpio.h>	2023-01-13 16:51:36 +00:00
mt8186	soc/mediatek: Include <gpio.h> instead of <soc/gpio.h>	2023-01-13 16:51:36 +00:00
mt8188	soc/mediatek/mt8188: Fix audio sampling rate	2023-02-22 03:18:17 +00:00
mt8192	soc/mediatek: Include <gpio.h> instead of <soc/gpio.h>	2023-01-13 16:51:36 +00:00
mt8195	soc/mediatek: Include <gpio.h> instead of <soc/gpio.h>	2023-01-13 16:51:36 +00:00