This patch updates the MTLRVP flash layout to allow CSE Lite FW
update and accommodate multiple ESx SoC stepping blobs.
SI_BIOS:
SI_EC: Removed
RW_SECTION_A/B: Increased by ~1.9MB.
RW_LEGACY: Reduce to 1MB.
RW_MISC: Reduce to 152KB.
- Drop RW_SPD_CACHE
- Optimize other sections
Additionally, moved RW_LEGACY under extended BIOS region.
For chromeos-debug-fsp.fmd
SI_BIOS:
RW_SECTION_A/B: Increased by ~1.2MB.
RW_LEGACY: Dropped
RW_MISC: Reduce to 152KB.
- Drop RW_SPD_CACHE
- Optimize other sections
BUG=b:271407315
TEST=Able to enable CSE update on MTLRVP and have free space
to add one more PUNIT FW to support different SoC stepping.
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: I8cfba861e6d3122b0795a5a8e589c67cebad9762
Reviewed-on: https://review.coreboot.org/c/coreboot/+/73378
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
fb1b192cf1